initialisation.c

This directory contains an example ADSP-BF535 subroutine that demonstrates the initialization of t

#include "BF535 Talkthrough.h"

//--------------------------------------------------------------------------//
// Function:	Init_Flags													//
//																			//
// Parameters:	None														//
//																			//
// Return:		None														//
//																			//
// Description:	Configure PF15 as output.									//
//--------------------------------------------------------------------------//
void Init_Flags(void)
{
	// configure PF15 as output (connected to codec reset)
	*pFIO_DIR = 0x8000;
}

//--------------------------------------------------------------------------//
// Function:	Init_SPORT0													//
//																			//
// Parameters:	None														//
//																			//
// Return:		None														//
//																			//
// Description:	SPORT0 is configured for Descriptor Multichannel mode,		//
//				using 16 channels and a word length of 16 bit. The serial	//
//				clock is provided by the codec, whereas the DSP generates	//
//				the frame sync internally with a frame size of 256 bit.		//
//				DMA transfer is used to transfer data from/to SPORT0.		//
//				SPORT0 will be enabled in function Init_Codec after codec	//
//				reset.														//
//--------------------------------------------------------------------------//
void Init_SPORT0(void)
{
	// configure Multichannel mode
	*pSPORT0_MTCS0 = 0xffff;					// enable 16 transmit channels
	*pSPORT0_MTCS1 = 0x0000;
	*pSPORT0_MTCS2 = 0x0000;
	*pSPORT0_MTCS3 = 0x0000;
	*pSPORT0_MTCS4 = 0x0000;
	*pSPORT0_MTCS5 = 0x0000;
	*pSPORT0_MTCS6 = 0x0000;
	*pSPORT0_MTCS7 = 0x0000;
	*pSPORT0_MRCS0 = 0xffff;					// enable 16 receive channels
	*pSPORT0_MRCS1 = 0x0000;
	*pSPORT0_MRCS2 = 0x0000;
	*pSPORT0_MRCS3 = 0x0000;
	*pSPORT0_MRCS4 = 0x0000;
	*pSPORT0_MRCS5 = 0x0000;
	*pSPORT0_MRCS6 = 0x0000;
	*pSPORT0_MRCS7 = 0x0000;
	*pSPORT0_MCMC1 = 0x0023;					// frame size 16 words; enable Multichannel mode
	*pSPORT0_MCMC2 = 0x000C;

	// configure SPORT0 receiver and transmitter; SPORT0 is enabled in Init_Codec after codec reset
	*pSPORT0_RFSDIV		= 0x00FF;				// frame sync every 256 bit
	*pSPORT0_RX_CONFIG	= 0x03E0;				// 16-bit words; internal frame sync
	*pSPORT0_TX_CONFIG	= 0x01E0;				// 16-bit words

	// set base pointer for DMA Descriptors (used for all Descriptors)
	*pDMA_DBP = (unsigned short)((unsigned int)sSPORT0_TX_Descriptor >> 16);

	// configure SPORT0 TX Descriptor block in memory
	sSPORT0_TX_Descriptor[0] = 0x8005;
	sSPORT0_TX_Descriptor[1] = AC97_FRAME_SIZE;
	sSPORT0_TX_Descriptor[2] = (unsigned short)((unsigned int)sSPORT0_TX_Buffer & 0xffff);
	sSPORT0_TX_Descriptor[3] = (unsigned short)((unsigned int)sSPORT0_TX_Buffer >> 16);
	sSPORT0_TX_Descriptor[4] = (unsigned short)((unsigned int)sSPORT0_TX_Descriptor & 0xffff);

	// configure SPORT0 RX Descriptor block in memory
	sSPORT0_RX_Descriptor[0] = 0x8007;
	sSPORT0_RX_Descriptor[1] = AC97_FRAME_SIZE;
	sSPORT0_RX_Descriptor[2] = (unsigned short)((unsigned int)sSPORT0_RX_Buffer & 0xffff);
	sSPORT0_RX_Descriptor[3] = (unsigned short)((unsigned int)sSPORT0_RX_Buffer >> 16);
	sSPORT0_RX_Descriptor[4] = (unsigned short)((unsigned int)sSPORT0_RX_Descriptor & 0xffff);

	// enable SPORT0 TX/RX DMA transfers
	*pSPORT0_NEXT_DESCR_TX	= (unsigned short)((unsigned int)sSPORT0_TX_Descriptor & 0xffff);
	*pSPORT0_NEXT_DESCR_RX	= (unsigned short)((unsigned int)sSPORT0_RX_Descriptor & 0xffff);
	*pSPORT0_CONFIG_DMA_TX	= 0x0001;
	*pSPORT0_CONFIG_DMA_RX	= 0x0001;
}

//--------------------------------------------------------------------------//
// Function:	Init_Interrupts												//
//																			//
// Parameters:	None														//
//																			//
// Return:		None														//
//																			//
// Description:	Configure SPORT0 TX and RX interrupts.						//
//--------------------------------------------------------------------------//
void Init_Interrupts(void)
{
	// configure interrupts
	*pSIC_IAR0 = 0xff21ffff;					// SPORT0 RX = ID 1; SPORT0 TX = ID 2
	*pSIC_IAR1 = 0xffffffff;
	*pSIC_IAR2 = 0xffffffff;
	register_handler(ik_ivg8, SPORT0_RX_ISR);	// assign SPORT0 RX ISR to interrupt vector 8
	register_handler(ik_ivg9, SPORT0_TX_ISR);	// assign SPORT0 TX ISR to interrupt vector 9
	*pSIC_IMASK = 0x00000030;					// enable SPORT0 TX and RX interrupt

// for chip revisions >= 1.0 remove the following instruction (needed for anomaly "IMASK bit polarity")
//*pSIC_IMASK = 0xffffffcf;
}

//--------------------------------------------------------------------------//
// Function:	Init_Codec													//
//																			//
// Parameters:	None														//
//																			//
// Return:		None														//
//																			//
// Description:	This function resets the codec, enables SPORT0 and waits	//
//				until the codec is ready (first bit in frame is '1').		//
//				It will then replace the SPORT0 RX ISR dummy function with	//
//				Wait_For_Codec_Init, which places a new register value into	//
//				the transmit buffer every time a SPORT0 RX interrupt occurs.//
//--------------------------------------------------------------------------//
void Init_Codec(void)
{
	volatile int iCounter;

	// reset codec
	*pFIO_FLAG_C = 0x8000;						// clear PF15 (assert reset for codec)
	for(iCounter = 0x0000; iCounter < 0x0fa0; iCounter++) iCounter = iCounter;
												// hold codec for at least 1 us in reset
	*pFIO_FLAG_S = 0x8000;						// set PF15 (deassert reset for codec)
	for(iCounter = 0x0000; iCounter < 0xffff; iCounter++) iCounter = iCounter;
												// delay to recover from reset

	// enable SPORT0 data transmission
	*pSPORT0_RX_CONFIG = *pSPORT0_RX_CONFIG | 0x0001;	// enable SPORT0 receiver
	ssync();
	*pSPORT0_TX_CONFIG = *pSPORT0_TX_CONFIG | 0x0001;	// enable SPORT0 transmitter
	ssync();

	//wait for frame valid flag from codec (first bit in receive buffer)
	while(!(sSPORT0_RX_Buffer[SLOT_TAG] & 0x8000));

	// now start sending configuration registers to codec
	pSPORT0_RX_ISR_Handling = Wait_For_Codec_Init;
}