📄 svgen_dq.lst
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457 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
458 ;--------------------------------------------------------------------------------
459
460 009e 8ba0 MAR *+ ; AR2++. Now AR2 -> tb
461 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR3.
462 ;--------------------------------------------------------------------------------
463 009f 90ab SACL *+,AR3 ; Store tb
464 ; ARP=AR3. AR0->FR1 AR2->tc AR3->FR3.
465 ;--------------------------------------------------------------------------------
466 00a0 20aa ADD *+,AR2 ; ACC = tb + t1.
467 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Mon Aug 18 20:35:52 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 10
468 ;--------------------------------------------------------------------------------
469 00a1 908b SACL *,AR3 ; Store tc = tb + t1.
470 ; ARP=AR3. AR0->FR1 AR2->tc AR3->FR4.
471 ;--------------------------------------------------------------------------------
472 00a2 208a ADD *,AR2 ; ACC = tc + t2.
473 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
474 ;--------------------------------------------------------------------------------
475 00a3 7c02 SBRK #2 ; Point AR2 to ta.
476 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
477 ;--------------------------------------------------------------------------------
478 00a4 90a0 SACL *+ ; Store ta.
479 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
480 ;--------------------------------------------------------------------------------
481 00a5 7980 B SV_POST_PROCESS
00a6 00bc'
482 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
483 ;--------------------------------------------------------------------------------
484 ; Sector Subroutine #6. On arrival :
485 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
486 ;--------------------------------------------------------------------------------
487 00a7 7c01 SECTOR_SR6: SBRK #1 ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR3.
488
489 00a8 10ab LACC *+,AR3 ; ACC = Y
490 ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
491 ;--------------------------------------------------------------------------------
492 00a9 be02 NEG ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
493 ;--------------------------------------------------------------------------------
494 00aa 90a8 SACL *+,AR0 ; Store t1 = -Y. ( FR3 = t1.)
495 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR4.
496 ;--------------------------------------------------------------------------------
497 00ab 109b LACC *-,AR3 ; ACC = Z.
498 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
499 ;--------------------------------------------------------------------------------
500 00ac be02 NEG ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
501 ;--------------------------------------------------------------------------------
502 00ad 9090 SACL *- ; Store t2 = -Z. ( FR4 = t2.)
503 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
504 ;--------------------------------------------------------------------------------
505 00ae bf80 LACC #7fffh ; ACCL= 1 (Q15).
00af 7fff
506 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
507 ;--------------------------------------------------------------------------------
508 00b0 30a0 SUB *+ ; ACC = 1-t1.
509 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
510 ;--------------------------------------------------------------------------------
511 00b1 309a SUB *-,AR2 ; ACC = 1-t1=t2.
512 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
513 ;--------------------------------------------------------------------------------
514 00b2 be0a SFR ; ACC = (1-t1=t2)/2.
515 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
516 ;--------------------------------------------------------------------------------
517 00b3 7802 ADRK #2 ; AR2+=2. Now AR2 -> tc
518 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR3.
519 ;--------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Mon Aug 18 20:35:52 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 11
520 00b4 908b SACL *,AR3 ; Store tc
521 ; ARP=AR3. AR0->FR1 AR2->tc AR3->FR3.
522 ;--------------------------------------------------------------------------------
523 00b5 20aa ADD *+,AR2 ; ACC = tc + t1.
524 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
525 ;--------------------------------------------------------------------------------
526 00b6 7c02 SBRK #2 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
527 ;--------------------------------------------------------------------------------
528 00b7 90ab SACL *+,AR3 ; Store ta = tc + t1.
529 ; ARP=AR3. AR0->FR1 AR2->tb AR3->FR4.
530 ;--------------------------------------------------------------------------------
531 00b8 208a ADD *,AR2 ; ACC = ta + t2.
532 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
533 ;--------------------------------------------------------------------------------
534 00b9 9080 SACL * ; Store tb.
535 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
536 ;--------------------------------------------------------------------------------
537 00ba 7980 B SV_POST_PROCESS
00bb 00bc'
538 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
539 ;--------------------------------------------------------------------------------
540
541
542 00bc SV_POST_PROCESS: ; On arrival: ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
543
544 ; Multiply tb by 2 and subtract offset = 1/2. for ta,tb,tc.
545 ;-------------------------------------------------------------------------------
546 00bc 8b90 MAR *- ; AR2--
547 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
548 ;-------------------------------------------------------------------------------
549 00bd 1080 LACC * ; Get ta
550 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
551 ;-------------------------------------------------------------------------------
552 00be bfa0 SUB #3FFFh ; Subtract offset.
00bf 3fff
553 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
554 ;-------------------------------------------------------------------------------
555 00c0 91a0 SACL *+,1 ; Store (ta-0.5)*2
556 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
557 ;-------------------------------------------------------------------------------
558 00c1 1080 LACC * ; Get tb
559 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
560 ;-------------------------------------------------------------------------------
561 00c2 bfa0 SUB #3FFFh ; Subtract offset.
00c3 3fff
562 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
563 ;-------------------------------------------------------------------------------
564 00c4 91a0 SACL *+,1 ; Store (tb-0.5)*2
565 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
566 ;-------------------------------------------------------------------------------
567 00c5 1080 LACC * ; Get tc
568 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
569 ;-------------------------------------------------------------------------------
570 00c6 bfa0 SUB #3FFFh ; Subtract offset.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Mon Aug 18 20:35:52 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 12
00c7 3fff
571 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
572 ;-------------------------------------------------------------------------------
573 00c8 9180 SACL *,1 ; Store (tc-0.5)*2
574 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
575 ;-------------------------------------------------------------------------------
576 00c9 DUMMY ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
577 ;-------------------------------------------------------------------------------
578 00c9 __svgendq_exit:
579 00c9 8b89 MAR *,AR1 ; can be removed if this condition is met on
580 ; every path to this code.
581
582
583 00ca bf00 SPM 0
584 00cb be42 CLRC OVM
585
586
587 00cc 7c06 SBRK #(__svgendq_framesize+1)
588 00cd 0090 LAR AR0,*-
589 00ce 7680 PSHD *
590 00cf ef00 RET
591
592 ;-------------------------------------------------------------------------------
593 ;SVPWM Sector routine jump table (Used to ref with BACC instruction
594 ;-------------------------------------------------------------------------------
595 00d0 SECTOR_TABLE_BASE:
596
597 00d0 00c9' SR0 .word DUMMY
598 00d1 0048' SR1 .word SECTOR_SR1
599 00d2 005a' SR2 .word SECTOR_SR2
600 00d3 006d' SR3 .word SECTOR_SR3
601 00d4 007f' SR4 .word SECTOR_SR4
602 00d5 0093' SR5 .word SECTOR_SR5
603 00d6 00a7' SR6 .word SECTOR_SR6
604 00d7 00c9' SR7 .word DUMMY
605
606
No Errors, No Warnings
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