svgen_dq.lst

TI公司24X系列DSP控制永磁同步电机PMSM

     304 0065 908b                  SACL    *,AR3  ; Store ta
     305                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     306            ;--------------------------------------------------------------------------------
     307 0066 20aa                  ADD     *+,AR2  ; ACC = ta + t1.
     308                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
     309            ;--------------------------------------------------------------------------------
     310 0067 7802                  ADRK    #2      ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
     311            ;--------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Mon Aug 18 20:35:52 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
svgen_dq.asm                                                         PAGE    7

     312 0068 909b                  SACL    *-,AR3  ; Store tc = ta + t1.
     313                                            ; ARP=AR3. AR0->FR1 AR2->tb AR3->FR4.
     314            ;--------------------------------------------------------------------------------
     315 0069 208a                  ADD     *,AR2   ; ACC = tc + t2.
     316                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     317            ;--------------------------------------------------------------------------------
     318 006a 9080                  SACL    *       ; Store tb.
     319                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     320            ;--------------------------------------------------------------------------------
     321 006b 7980                  B       SV_POST_PROCESS
         006c 00bc' 
     322            ;--------------------------------------------------------------------------------
     323            ; Sector Subroutine #3. On arrival : 
     324            ;                                 ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
     325            ;--------------------------------------------------------------------------------
     326 006d 109b  SECTOR_SR3:     LACC    *-,AR3  ; ACC = Z
     327                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     328            ;--------------------------------------------------------------------------------
     329 006e be02                  NEG             ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     330            ;--------------------------------------------------------------------------------
     331 006f 90a8                  SACL    *+,AR0  ; Store t1 = -Z. ( FR3 = t1.)
     332                                            ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR4.
     333            ;--------------------------------------------------------------------------------
     334 0070 8b90                  MAR     *-      ; ARP=AR0. AR0->FR0 AR2->ta AR3->FR4.
     335            ;--------------------------------------------------------------------------------
     336            
     337 0071 10ab                  LACC    *+,AR3  ; ACC = X.
     338                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     339            ;--------------------------------------------------------------------------------
     340 0072 9090                  SACL    *-      ; Store t2 = X. ( FR4 = t2.)
     341                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     342            ;--------------------------------------------------------------------------------
     343 0073 bf80                  LACC    #7fffh  ; ACCL= 1 (Q15).
         0074 7fff  
     344                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     345            ;--------------------------------------------------------------------------------
     346 0075 30a0                  SUB     *+      ; ACC = 1-t1.
     347                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     348            ;--------------------------------------------------------------------------------
     349 0076 309a                  SUB     *-,AR2  ; ACC = 1-t1=t2.
     350                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     351            ;--------------------------------------------------------------------------------
     352 0077 be0a                  SFR             ; ACC = (1-t1=t2)/2.
     353                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     354            ;--------------------------------------------------------------------------------
     355 0078 90ab                  SACL    *+,AR3  ; Store ta
     356                                            ; ARP=AR3. AR0->FR1 AR2->tb AR3->FR3.
     357            ;--------------------------------------------------------------------------------
     358 0079 20aa                  ADD     *+,AR2  ; ACC = ta + t1
     359                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     360            ;--------------------------------------------------------------------------------
     361 007a 90ab                  SACL    *+,AR3   ; Store tb = ta + t1.
     362                                            ; ARP=AR3. AR0->FR1 AR2->tc AR3->FR4.
     363            ;--------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Mon Aug 18 20:35:52 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
svgen_dq.asm                                                         PAGE    8

     364 007b 208a                  ADD     *,AR2   ; ACC = tb + t2.
     365                                            ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
     366            ;--------------------------------------------------------------------------------
     367 007c 9090                  SACL    *-      ; Store tc.
     368                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     369            ;--------------------------------------------------------------------------------
     370 007d 7980                  B       SV_POST_PROCESS
         007e 00bc' 
     371                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     372            ;--------------------------------------------------------------------------------
     373            
     374            ;--------------------------------------------------------------------------------
     375            ; Sector Subroutine #4. On arrival : 
     376            ;                                 ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
     377            ;--------------------------------------------------------------------------------
     378 007f 7c02  SECTOR_SR4:     SBRK    #2      ; ARP=AR0. AR0->FR0 AR2->ta AR3->FR3.
     379            ;--------------------------------------------------------------------------------
     380 0080 10ab                  LACC    *+,AR3  ; ACC = X
     381                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     382            ;--------------------------------------------------------------------------------
     383 0081 be02                  NEG             ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     384            ;--------------------------------------------------------------------------------
     385 0082 90a8                  SACL    *+,AR0  ; Store t1 = -X. ( FR3 = t1.)
     386                                            ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR4.
     387            ;--------------------------------------------------------------------------------
     388 0083 8ba0                  MAR     *+      ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR4.
     389            ;--------------------------------------------------------------------------------
     390 0084 109b                  LACC    *-,AR3  ; ACC = Z.
     391                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     392            ;--------------------------------------------------------------------------------
     393 0085 9090                  SACL    *-      ; Store t2 = Y. ( FR4 = t2.)
     394                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     395            ;--------------------------------------------------------------------------------
     396 0086 bf80                  LACC    #7fffh  ; ACCL= 1 (Q15).
         0087 7fff  
     397                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     398            ;--------------------------------------------------------------------------------
     399 0088 30a0                  SUB     *+      ; ACC = 1-t1.
     400                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     401            ;--------------------------------------------------------------------------------
     402 0089 309a                  SUB     *-,AR2  ; ACC = 1-t1=t2.
     403                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     404            ;--------------------------------------------------------------------------------
     405 008a be0a                  SFR             ; ACC = (1-t1=t2)/2.
     406                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     407            ;--------------------------------------------------------------------------------
     408 008b 7802                  ADRK    #2      ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR3.
     409            ;--------------------------------------------------------------------------------
     410 008c 909b                  SACL    *-,AR3  ; Store tc
     411                                            ; ARP=AR3. AR0->FR1 AR2->tb AR3->FR3.
     412            ;--------------------------------------------------------------------------------
     413 008d 20aa                  ADD     *+,AR2  ; ACC = tc + t1
     414                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     415            ;--------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00  Mon Aug 18 20:35:52 2003
Copyright (c) 1987-1999  Texas Instruments Incorporated 
svgen_dq.asm                                                         PAGE    9

     416 008e 909b                  SACL    *-,AR3  ; Store tb = tc + t1.
     417                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     418            ;--------------------------------------------------------------------------------
     419 008f 208a                  ADD     *,AR2   ; ACC = tb + t2.
     420                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
     421            ;--------------------------------------------------------------------------------
     422 0090 90a0                  SACL    *+      ; Store ta.
     423                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     424            ;--------------------------------------------------------------------------------
     425 0091 7980                  B       SV_POST_PROCESS
         0092 00bc' 
     426                                            ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
     427            ;--------------------------------------------------------------------------------
     428            ; Sector Subroutine #5. On arrival : 
     429            ;                                 ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
     430            ;--------------------------------------------------------------------------------
     431 0093 7c02  SECTOR_SR5:     SBRK    #2      ; ARP=AR0. AR0->FR0 AR2->ta AR3->FR3.
     432            
     433 0094 10ab                  LACC    *+,AR3  ; ACC = X
     434                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     435            ;--------------------------------------------------------------------------------
     436 0095 90a8                  SACL    *+,AR0  ; Store t1 = X. ( FR3 = t1.)
     437                              ;      ^      ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR4.
     438            ;--------------------------------------------------------------------------------
     439 0096 108b                  LACC    *,AR3   ; ACC = Y.
     440                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     441            ;--------------------------------------------------------------------------------
     442 0097 be02                  NEG             ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     443            ;--------------------------------------------------------------------------------
     444 0098 9090                  SACL    *-      ; Store t2 = -Y. ( FR4 = t2.)
     445                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     446            ;--------------------------------------------------------------------------------
     447 0099 bf80                  LACC    #7fffh  ; ACCL= 1 (Q15).
         009a 7fff  
     448                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
     449            ;--------------------------------------------------------------------------------
     450 009b 30a0                  SUB     *+      ; ACC = 1-t1.
     451                                            ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
     452            ;--------------------------------------------------------------------------------
     453 009c 309a                  SUB     *-,AR2  ; ACC = 1-t1=t2.
     454                                            ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
     455            ;--------------------------------------------------------------------------------
     456 009d be0a                  SFR             ; ACC = (1-t1=t2)/2.