📄 svgen_dq.lst
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152 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
153
154 002d 1080 vref2_neg: LACC * ; Load va
155 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
156 ;--------------------------------------------------------------------------------
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Mon Aug 18 20:35:52 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 4
157 002e e3cc BCND vref1_neg,LEQ
002f 0035'
158 ; If vb<0 then do not set bit 1 of sector.
159 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
160 ;--------------------------------------------------------------------------------
161 0030 8b8b MAR *,AR3 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
162 ;--------------------------------------------------------------------------------
163 0031 1080 LACC * ; Get sector code.
164 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
165 ;--------------------------------------------------------------------------------
166 0032 bfc0 OR #1 ; Set bit 0.
0033 0001
167 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
168 ;--------------------------------------------------------------------------------
169 0034 9088 SACL *,AR0 ; Store sector code
170 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
171 0035 vref1_neg:
172
173 ;--------------------------------------------------------------------------------
174 0035 8b8a MAR *,AR2 ; ARP=AR2. AR0->FR0 AR2->q AR3->FR3
175 ;--------------------------------------------------------------------------------
176 0036 1098 LACC *-,AR0 ; ACC = q.
177 ; ARP=AR0. AR0->FR0 AR2->d AR3->FR3
178 ;--------------------------------------------------------------------------------
179 0037 90a0 SACL *+ ; Store FR0=X=q.
180 ; ARP=AR0. AR0->FR1 AR2->d AR3->FR3
181 ;--------------------------------------------------------------------------------
182 0038 ae80 SPLK #28377,* ;FR1 = sqrt(3) / 2.
0039 6ed9
183 ; ARP=AR0. AR0->FR1 AR2->d AR3->FR3
184 ;--------------------------------------------------------------------------------
185 003a 738a LT *,AR2 ; TREG = sqrt(3) / 2.
186 ; ARP=AR2. AR0->FR1 AR2->d AR3->FR3
187 ;--------------------------------------------------------------------------------
188 003b 54a0 MPY *+ ; PREG = d * sqrt(3) / 2.
189 ; ARP=AR2. AR0->FR1 AR2->q AR3->FR3
190 ;--------------------------------------------------------------------------------
191 003c be03 PAC ; ACC = d * sqrt(3) / 2.
192 ; ARP=AR2. AR0->FR1 AR2->q AR3->FR3
193 ;--------------------------------------------------------------------------------
194 003d 2f88 ADD *,15,AR0 ; ACCH= q/2 + d * sqrt(3) / 2.
195 ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
196 ;--------------------------------------------------------------------------------
197 003e 98aa SACH *+,AR2 ; Store FR1 = Y = q/2 + d * sqrt(3) / 2.
198 ; ARP=AR2. AR0->FR2 AR2->q AR3->FR3
199 ;--------------------------------------------------------------------------------
200 003f 1fa8 LACC *+,15,AR0 ; ACCH = q/2.
201 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
202 ;--------------------------------------------------------------------------------
203 0040 be05 SPAC ; ACCH = q/2 - d * sqrt(3) / 2.
204 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
205 ;--------------------------------------------------------------------------------
206 0041 988b SACH *,AR3 ; Store FR2 = Z = q/2 - d * sqrt(3) / 2.
207 ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Mon Aug 18 20:35:52 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 5
208 ;--------------------------------------------------------------------------------
209 0042 10a0 LACC *+ ; Load sector #.
210 ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
211 ;--------------------------------------------------------------------------------
212 0043 bf90 ADD #SECTOR_TABLE_BASE
0044 00d0'
213 ;--------------------------------------------------------------------------------
214 0045 a680 TBLR * ; FR3 = Sector subroutine address.
215 ; ARP=AR3. AR0->FR2 AR2->ta AR3->FR3.
216 ;--------------------------------------------------------------------------------
217 0046 1088 LACC *,AR0 ; ACC = Sector subroutine address.
218 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
219 ;--------------------------------------------------------------------------------
220 0047 be20 BACC ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
221 ;--------------------------------------------------------------------------------
222 ; Sector Subroutine #1. On arrival :
223 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
224 ;--------------------------------------------------------------------------------
225 0048 109b SECTOR_SR1: LACC *-,AR3 ; ACC = Z
226 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
227 ;--------------------------------------------------------------------------------
228 0049 90a8 SACL *+,AR0 ; Store t1 = Z. ( FR3 = t1.)
229 ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR4.
230 ;--------------------------------------------------------------------------------
231 004a 108b LACC *,AR3 ; ACC = Y.
232 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
233 ;--------------------------------------------------------------------------------
234 004b 9090 SACL *- ; Store t2 = Y. ( FR4 = t2.)
235 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
236 ;--------------------------------------------------------------------------------
237 004c bf80 LACC #7fffh ; ACCL= 1 (Q15).
004d 7fff
238 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
239 ;--------------------------------------------------------------------------------
240 004e 30a0 SUB *+ ; ACC = 1-t1.
241 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
242 ;--------------------------------------------------------------------------------
243 004f 309a SUB *-,AR2 ; ACC = 1-t1=t2.
244 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
245 ;--------------------------------------------------------------------------------
246 0050 be0a SFR ; ACC = (1-t1=t2)/2.
247 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
248 ;--------------------------------------------------------------------------------
249 0051 8ba0 MAR *+ ; AR2++. Now AR2 -> tb
250 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR3.
251 ;--------------------------------------------------------------------------------
252 0052 909b SACL *-,AR3 ; Store tb
253 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
254 ;--------------------------------------------------------------------------------
255 0053 20aa ADD *+,AR2 ; ACC = tb + t1.
256 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
257 ;--------------------------------------------------------------------------------
258 0054 908b SACL *,AR3 ; Store ta = tb + t1.
259 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Mon Aug 18 20:35:52 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 6
260 ;--------------------------------------------------------------------------------
261 0055 208a ADD *,AR2 ; ACC = tb + t2.
262 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR4.
263 ;--------------------------------------------------------------------------------
264 0056 7802 ADRK #2 ; Point AR2 to tc.
265 ; ARP=AR2. AR0->FR1 AR2->tc AR3->FR4.
266 ;--------------------------------------------------------------------------------
267 0057 9090 SACL *- ; Store tc.
268 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
269 ;--------------------------------------------------------------------------------
270 0058 7980 B SV_POST_PROCESS
0059 00bc'
271 ; ARP=AR2. AR0->FR1 AR2->tb AR3->FR4.
272 ;--------------------------------------------------------------------------------
273 ; Sector Subroutine #2. On arrival :
274 ; ARP=AR0. AR0->FR2 AR2->ta AR3->FR3.
275 ;--------------------------------------------------------------------------------
276 005a 8b90 SECTOR_SR2: MAR *- ; ARP=AR0. AR0->FR1 AR2->ta AR3->FR3.
277 ;--------------------------------------------------------------------------------
278 005b 109b LACC *-,AR3 ; ACC = Y
279 ; ARP=AR3. AR0->FR0 AR2->ta AR3->FR3.
280 ;--------------------------------------------------------------------------------
281 005c 90a8 SACL *+,AR0 ; Store t1 = Y. ( FR3 = t1.)
282 ; ARP=AR0. AR0->FR0 AR2->ta AR3->FR4.
283 ;--------------------------------------------------------------------------------
284 005d 10ab LACC *+,AR3 ; ACC = X.
285 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
286 ;--------------------------------------------------------------------------------
287 005e be02 NEG ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
288 ;--------------------------------------------------------------------------------
289 005f 9090 SACL *- ; Store t2 = -X. ( FR4 = t2.)
290 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
291 ;--------------------------------------------------------------------------------
292 0060 bf80 LACC #7fffh ; ACCL= 1 (Q15).
0061 7fff
293 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR3.
294 ;--------------------------------------------------------------------------------
295 0062 30a0 SUB *+ ; ACC = 1-t1.
296 ; ARP=AR3. AR0->FR1 AR2->ta AR3->FR4.
297 ;--------------------------------------------------------------------------------
298 0063 309a SUB *-,AR2 ; ACC = 1-t1-t2.
299 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
300 ;--------------------------------------------------------------------------------
301 0064 be0a SFR ; ACC = (1-t1-t2)/2.
302 ; ARP=AR2. AR0->FR1 AR2->ta AR3->FR3.
303 ;--------------------------------------------------------------------------------
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