📄 svgen_dq.lst
字号:
C:\TIC2XX\C2000\CGTOOLS\BIN\DSPA.EXE -q -v2xx -gs svgen_dq.asm -o ..\obj\svgen_dq.obj -l ..\temp\svgen_dq.lst
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Mon Aug 18 20:35:52 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 1
1 ;=====================================================================================
2 ; File name: SVGEN_DQ.ASM
3 ;
4 ; Originator: Digital Control Systems Group
5 ; Texas Instruments
6 ;
7 ; Description:
8 ; This file contains source for Space vector modulation dq -> SV(a,b,c).
9 ;=====================================================================================
10 ; History:
11 ;-------------------------------------------------------------------------------------
12 ; 9-15-2000 Release Rev 1.0
13 ; 8-18-2003 : Exit program safely for SECTOR0 and SECTOR7 (DUMMY location)
14 ;================================================================================
15 ; Applicability: F240,F241,C242,F243,F24xx. (Peripheral Independant).
16 ;================================================================================
17 ; Routine Name: svgendq Routine Type: C Callable
18 ;
19 ; Description:
20 ;
21 ; C prototype : int svgendq(struct SVGENDQ *p);
22 ;
23 ; The struct is defined as follows:
24 ;
25 ; typedef struct SVGENDQ { int d,q,ta,tb,tc ; };
26 ;
27 ; Frame Usage Details:
28 ; | a | b | c | d
29 ;____________|_____________|_______________|____________|_____________
30 ; FR0 | va | X | X | X
31 ; FR1 | vb | Y | Y | Y
32 ; FR2 | vc | Z | Z | Z
33 ; FR3 | sector | sector | sr_address | t1
34 ; FR4 | | | | t2
35
36
37
38 ;================================================================================
39 .def _svgendq_calc
40 ;================================================================================
41 0005 __svgendq_framesize .set 0005h
42 ;================================================================================
43 0000 _svgendq_calc:
44 0000 8aa0 POPD *+
45 0001 80a0 SAR AR0,*+
46 0002 8180 SAR AR1,*
47 0003 b005 LARK AR0,__svgendq_framesize
48 0004 00e8 LAR AR0,*0+,AR0
49
50 ;================================================================================
51 0005 7c03 SBRK #3 ; Point AR0 to the first argument.
52 ;--------------------------------------------------------------------------------
53 0006 0280 LAR AR2,*
54 ; get the argument in AR2.
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Mon Aug 18 20:35:52 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 2
55 ; ARP=AR0. AR0->([FR0-3]=Argument 1) and AR2->d
56 0007 7803 ADRK #3 ; ARP=AR0. AR0->FR0 and AR2->d
57
58 0008 8b8a MAR *,AR2 ; ARP=AR2. AR0->FR0 and AR2->d
59 ;--------------------------------------------------------------------------------
60 0009 bf01 SPM 1 ; Set product shift mode to one.
61 ; ARP=AR2. AR0->FR0 and AR2->d
62 ;--------------------------------------------------------------------------------
63 000a be47 SETC SXM ; Turn sign extension mode on.
64 ; ARP=AR2. AR0->FR0 and AR2->d
65
66 ;--------------------------------------------------------------------------------
67 000b 7801 ADRK #1 ; ARP=AR2. AR0->FR0 and AR2->q
68 ;--------------------------------------------------------------------------------
69 000c 1098 LACC *-,AR0 ; Load q.
70 ; ARP=AR0. AR0->FR0 and AR2->d
71 ;--------------------------------------------------------------------------------
72 000d 90a0 SACL *+ ; Store va=q
73 ; ARP=AR0. AR0->FR1 and AR2->d
74 ;--------------------------------------------------------------------------------
75 000e ae80 SPLK #28377,*
000f 6ed9
76 ; FR1 = 0.5*qrt3.
77 ; ARP=AR0. AR0->FR1 and AR2->d
78 ;--------------------------------------------------------------------------------
79 0010 738a LT *,AR2 ; TREG = 0.5*qrt3.
80 ; ARP=AR2. AR0->FR1 and AR2->d
81 ;--------------------------------------------------------------------------------
82 0011 54a0 MPY *+ ; PREG = d * 0.5sqrt(3).
83 ; ARP=AR2. AR0->FR1 and AR2->q
84 ;--------------------------------------------------------------------------------
85 0012 b900 ZAC ; ACCH:ACCL=0.
86 ; ARP=AR2. AR0->FR1 and AR2->q
87 ;--------------------------------------------------------------------------------
88 0013 3f88 SUB *,15,AR0 ;ACC = -q/2
89 ; ARP=AR0. AR0->FR1 and AR2->q
90 ;--------------------------------------------------------------------------------
91 0014 be04 APAC ; ACC = -q/2 + d * 0.5sqrt(3)
92 ; ARP=AR0. AR0->FR1 and AR2->q
93 ;--------------------------------------------------------------------------------
94 0015 98a0 SACH *+ ; Store vb.
95 ; ARP=AR0. AR0->FR2 and AR2->q
96 ;--------------------------------------------------------------------------------
97 0016 be05 SPAC ; ACC = -q/2
98 ; ARP=AR0. AR0->FR2 and AR2->q
99 ;--------------------------------------------------------------------------------
100 0017 be05 SPAC ; ACC = -q/2 - (d * 0.5sqrt(3))
101 ; ARP=AR0. AR0->FR2 and AR2->q
102 ;--------------------------------------------------------------------------------
103 0018 98a0 SACH *+ ; Store vc.
104 ; ARP=AR0. AR0->FR3 and AR2->q
105 ;--------------------------------------------------------------------------------
106 0019 8080 SAR AR0,* ; FR3 = AR0 = &FR3.
107 ; ARP=AR0. AR0->FR3 and AR2->q
TMS320C1x/C2x/C2xx/C5x COFF Assembler Version 7.00 Mon Aug 18 20:35:52 2003
Copyright (c) 1987-1999 Texas Instruments Incorporated
svgen_dq.asm PAGE 3
108 ;--------------------------------------------------------------------------------
109 001a 039b LAR AR3,*-,AR3
110 ; AR3 = FR3 = &FR3.
111 ; i.e. now AR3 points to FR3.
112 ; ARP=AR3. AR0->FR2 AR2->q AR3->FR3
113 ;--------------------------------------------------------------------------------
114 001b ae88 SPLK #0,*,AR0
001c 0000
115 ; Store sector = FR3 = 0
116 ; ARP=AR0. AR0->FR2 AR2->q AR3->FR3
117 ;--------------------------------------------------------------------------------
118 001d 1090 LACC *- ; Load vc.
119 ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
120 ;--------------------------------------------------------------------------------
121 001e e3cc BCND vref3_neg,LEQ
001f 0025'
122 ; If vc<0 then do not set bit 2 of sector.
123 ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
124 ;--------------------------------------------------------------------------------
125 0020 8b8b MAR *,AR3 ; ARP=AR3. AR0->FR1 AR2->q AR3->FR3
126 ;--------------------------------------------------------------------------------
127 0021 1080 LACC * ; Get sector code.
128 ; ARP=AR3. AR0->FR1 AR2->q AR3->FR3
129 ;--------------------------------------------------------------------------------
130 0022 bfc0 OR #4 ; Set bit 2.
0023 0004
131 ; ARP=AR3. AR0->FR1 AR2->q AR3->FR3
132 ;--------------------------------------------------------------------------------
133 0024 9088 SACL *,AR0 ; Store sector code
134 ; ARP=AR0. AR0->FR1 AR2->q AR3->FR3
135 ;--------------------------------------------------------------------------------
136 0025 1090 vref3_neg: LACC *- ; Load vb
137 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
138 ;--------------------------------------------------------------------------------
139 0026 e3cc BCND vref2_neg,LEQ
0027 002d'
140 ; If vb<0 then do not set bit 1 of sector.
141 ; ARP=AR0. AR0->FR0 AR2->q AR3->FR3
142 ;--------------------------------------------------------------------------------
143 0028 8b8b MAR *,AR3 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
144 ;--------------------------------------------------------------------------------
145 0029 1080 LACC * ; Get sector code.
146 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
147 ;--------------------------------------------------------------------------------
148 002a bfc0 OR #2 ; Set bit 1.
002b 0002
149 ; ARP=AR3. AR0->FR0 AR2->q AR3->FR3
150 ;--------------------------------------------------------------------------------
151 002c 9088 SACL *,AR0 ; Store sector code
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -