com_trig.lst

TI公司24X系列DSP控制无刷直流电机

     129 002a 1107-                 LACC    Vb,1                    ;Fetch Vb
     130 002b 2007-                 ADD     Vb                      ;ACC=3*(Bemf + Neutral)
     131 002c 3004-                 SUB     neutral                 ;ACC=3*Bemf
     132 002d 9014-                 SACL    debug_Bemf                      
     133 002e e344                  BCND    CLR_NW_S1,LT            ;BEMF Still positive?
         002f 0034' 
     134            
     135 0030 7a80                  CALL    NOISE_WIN
         0031 00ac' 
     136 0032 7980                  B       ST_END
         0033 0094' 
     137            
     138 0034 ae0e- CLR_NW_S1       SPLK    #0h,noise_window_cntr
         0035 0000  
     139 0036 7980                  B       ST_END  
         0037 0094' 
     140            
     141            
     142            
     143                    ;State 2 - ZC for phase A
     144                    ;-----------------------
     145 0038       CT_STATE_BNC:
     146 0038 1106-                 LACC    Va,1                    ;Fetch Va
     147 0039 2006-                 ADD     Va                      ;ACC=3*(Bemf + Neutral)
TMS320C24xx COFF Assembler Version 7.04  Wed Dec 28 11:23:51 2005
Copyright (c) 1987-2003  Texas Instruments Incorporated 
com_trig.asm                                                         PAGE    4

     148 003a 3004-                 SUB     neutral                 ;ACC=3*Bemf
     149 003b 9014-                 SACL    debug_Bemf                      
     150 003c e304                  BCND    CLR_NW_S2,GT            ;BEMF Still positive?
         003d 0042' 
     151            
     152 003e 7a80                  CALL    NOISE_WIN
         003f 00ac' 
     153 0040 7980                  B       ST_END
         0041 0094' 
     154            
     155 0042 ae0e- CLR_NW_S2       SPLK    #0h,noise_window_cntr
         0043 0000  
     156 0044 7980                  B       ST_END  
         0045 0094' 
     157            
     158            
     159            
     160                    ;State 3 - ZC for phase C
     161                    ;-----------------------
     162 0046       CT_STATE_BNA:
     163 0046 1108-                 LACC    Vc,1                    ;Fetch Vc
     164 0047 2008-                 ADD     Vc                      ;ACC=3*(Bemf + Neutral)
     165 0048 3004-                 SUB     neutral                 ;ACC=3*Bemf
     166 0049 9014-                 SACL    debug_Bemf              
     167 004a e344                  BCND    CLR_NW_S3,LT            ;BEMF Still positive?
         004b 0050' 
     168            
     169 004c 7a80                  CALL    NOISE_WIN
         004d 00ac' 
     170 004e 7980                  B       ST_END
         004f 0094' 
     171            
     172 0050 ae0e- CLR_NW_S3       SPLK    #0h,noise_window_cntr
         0051 0000  
     173 0052 7980                  B       ST_END  
         0053 0094' 
     174            
     175            
     176            
     177                    ;State 4 - ZC for phase B
     178                    ;-----------------------
     179 0054       CT_STATE_CNA:
     180 0054 ae0d-                 SPLK    #0h, D30_done_flg       ;clear flag for delay calc in State 5
         0055 0000  
     181 0056 1107-                 LACC    Vb,1                    ;Fetch Vb
     182 0057 2007-                 ADD     Vb                      ;ACC=3*(Bemf + Neutral)
     183 0058 3004-                 SUB     neutral                 ;ACC=3*Bemf
     184 0059 9014-                 SACL    debug_Bemf                      
     185 005a e304                  BCND    CLR_NW_S4,GT            ;BEMF Still positive?
         005b 0060' 
     186            
     187 005c 7a80                  CALL    NOISE_WIN
         005d 00ac' 
     188 005e 7980                  B       ST_END
TMS320C24xx COFF Assembler Version 7.04  Wed Dec 28 11:23:51 2005
Copyright (c) 1987-2003  Texas Instruments Incorporated 
com_trig.asm                                                         PAGE    5

         005f 0094' 
     189            
     190 0060 ae0e- CLR_NW_S4       SPLK    #0h,noise_window_cntr
         0061 0000  
     191 0062 7980                  B       ST_END  
         0063 0094' 
     192            
     193            
     194            
     195                    ;State 5 - ZC for phase A
     196                    ;---------------------------------
     197 0064       CT_STATE_CNB:
     198 0064 1106-                 LACC    Va,1                    ;Fetch Va
     199 0065 2006-                 ADD     Va                      ;ACC=3*(Bemf + Neutral)
     200 0066 3004-                 SUB     neutral                 ;ACC=3*Bemf
     201 0067 9014-                 SACL    debug_Bemf              
     202 0068 e344                  BCND    CLR_NW_S5,LT            ;BEMF Still positive?
         0069 006e' 
     203            
     204 006a 7a80                  CALL    NOISE_WIN
         006b 00ac' 
     205 006c 7980                  B       DELAY_30
         006d 0070' 
     206            
     207 006e ae0e- CLR_NW_S5       SPLK    #0h,noise_window_cntr
         006f 0000  
     208            
     209            
     210                    ;Delay 30 deg calculator
     211                    ;---------------------------------
     212 0070       DELAY_30
     213 0070 100d-                 LACC    D30_done_flg
     214 0071 e308                  BCND    ST_END, NEQ             ;If gone through once, skip.
         0072 0094' 
     215            
     216 0073 1009-                 LACC    time_stamp_new          ;new-->old,  current-->new
     217 0074 900a-                 SACL    time_stamp_old  
     218            
     219 0075 bc00!                 ldp     #v_timer
     220 0076 1000!                 LACC    v_timer                 ;current-->new
     221            
     222 0077 bc00-                 ldp     #time_stamp_new
     223 0078 9009-                 SACL    time_stamp_new  
     224 0079 300a-                 SUB     time_stamp_old          ;Period = time_stamp_new - time_stamp_old
     225 007a e344                  BCND    NEG_DELTA, LT           ;If Period is negative, allow "wrapping"
         007b 007f' 
     226            
     227 007c 9005- POS_DELTA       SACL    rev_period              ;Delta = f(t2) - f(t1)
     228 007d 7980                  B       DELAY_DIV12
         007e 0082' 
     229            
     230 007f bf90  NEG_DELTA       ADD     #7FFFh                  ;Add 1 to Delta
         0080 7fff  
     231 0081 9005-                 SACL    rev_period              ;Delta = 1 + f(t2) - f(t1)
TMS320C24xx COFF Assembler Version 7.04  Wed Dec 28 11:23:51 2005
Copyright (c) 1987-2003  Texas Instruments Incorporated 
com_trig.asm                                                         PAGE    6

     232            
     233 0082       DELAY_DIV12:
     234 0082 1005-                 LACC    rev_period              ;Load the revolution time
     235 0083 ae0b-                 SPLK    #012,cmtn_delay
         0084 000c  
     236 0085 bb0f                  RPT     #15
     237 0086 0a0b-                 SUBC    cmtn_delay              ;Divide it by 12 (i.e. 30