📄 tusb3410.h
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#define DMACDR_ENDPOINT_MASK 0x07 // Endpoint Select Mask
#define DMACDR_ENDPOINT1 0x01 // Select Endpoint 1
#define DMACDR_ENDPOINT2 0x02 // Select Endpoint 2
#define DMACDR_ENDPOINT3 0x03 // Select Endpoint 3
#define DMACDR_ENDPOINT4 0x04 // Select Endpoint 4
#define DMACDR_ENDPOINT5 0x05 // Select Endpoint 5
#define DMACDR_ENDPOINT6 0x06 // Select Endpoint 6
#define DMACDR_ENDPOINT7 0x07 // Select Endpoint 7
#define DMACDR_TR 0x08 // DMA Direction (not used in UMP)
// 0:out, 1:in
#define DMACDR_XY 0x10 // XY Buffer Select (valid only when CNT=0)
// 0:X buffer 1:Y buffer
#define DMACDR_CNT 0x20 // DMA Continuous Transfer Control bit
// 0:Burst Mode, 1:Continuos Mode
#define DMACDR_INE 0x40 // DMA Interrupt Enable or Disable bit.
// 0:disable, 1:enable
#define DMACDR_EN 0x80 // DMA Channel Enable
// 0:disable, 1:enable
#define DMACSR_OVRUN 0x01 // Overrun Condition Bit. Set by DMA and Cleared by MCU
// 0: no overrun, 1:overrun
#define DMACSR_PPKT 0x01 // Overrun Condition Bit. Set by DMA and Cleared by MCU
// 0: no overrun(no partial packet) , 1:overrun
#define DMACSR_TXFT 0x02 // Transfer Timeout Condition. Cleared by MCU
// 0: no timeout, 1:timeout
#define DMACSR_TIMEOUT_MASK 0x7C // Select Timeout Value
#define DMACSR_TEN 0x80 // Transaction Timeout Conouter Enable or Disable Bit
// 0:disable(no timeout) 1:enable
// UART
// Line Control Register
#define LCR_WL_MASK 0x03 // Word Length Mask
#define LCR_WL_5BIT 0x00 // 5bit work length
#define LCR_WL_6BIT 0x01 // 6bit work length
#define LCR_WL_7BIT 0x02 // 7bit work length
#define LCR_WL_8BIT 0x03 // 8bit work length
#define LCR_STP 0x40 // Stop Bits
// 0:1 stop bit, 1:1.5 or 2 stop bits
#define LCR_PRTY 0x08 // Parity Bit
// 0:no parity, 1:parity bit is used.
#define LCR_EPRTY 0x10 // Odd Even Parity Bit
// 0:odd, 1:even
#define LCR_FPTY 0x20 // Force Parity Bit Slect
// 0:not forced, 1:parity bit forced
#define LCR_BRK 0x40 // Break Controll Bit
// 0:normal operation, 1:forces SOUT into break condition(logic 0)
#define LCR_FEN 0x80 // FIFO Enable
// 0: FIFO cleared and disable, 1: enable
#define FCRL_TXOF 0x01 // Transmitter Xon Xoff flow control
// 0:disable, 1:enable
#define FCRL_TXOA 0x02 // Xon-on-any Xoff flow control
// 0:disable, 1:enable
#define FCRL_CTS 0x04 // Transmitter CTS* Flow Control Enable Bit
// 0:disable, 1:enable
#define FCRL_DSR 0x04 // Transmitter DSR* Flow Control Enable Bit
// 0:disable, 1:enable
#define FCRL_RXOF 0x10 // Receiver Xon Xoff flow control
// 0:disable, 1:enable
#define FCRL_RTS 0x20 // Receiver RTS* Flow Controller Enable Bit
// 0:disable, 1:enable
#define FCRL_DTR 0x40 // Receiver DTR* Flow Controller Enable Bit
// 0:disable, 1:enable
#define FCRL_485E 0x80 // RS485 enable bit
// 0:normal, full duplex, 1:for RS485
#define MCR_URST 0x01 // UART Soft Reset
// 0:Mornal operation, 1:UART Reset
#define MCR_RCVE 0x02 // receiver enable bit
// 0:disable, 1:enable
#define MCR_LOOP 0x04 // Normal Loopback Mode Select
// 0:normal operation 1:enable loopback mode
//#define MCR_IEN 0x08 // Global UART Interrupt Enable Bit
// // 0:disable, 1:enable
#define MCR_DTR 0x10 // Set DTR*
// 0:set DTR* high, 1:set DTR* low
#define MCR_RTS 0x20 // Set RTS*
// 0:set RTS* high, 1:set RTS* low
#define MCR_LRI 0x40 // Used in loop-back mode only.
// 0: MSR[6]=0, 1:MSR[6]=1
#define MCR_LCD 0x40 // Used in loop-back mode only.
// 0: MSR[7]=0, 1:MSR[7]=1
#define LSR_OVR 0x01 // Overrun Condition
// 0:no overrun, 1:overrun
#define LSR_PTE 0x02 // Parity Condition
// 0:no parity error, 1:parity error
#define LSR_FRE 0x04 // Framing Condition
// 0:no frame error, 1:frame error
#define LSR_BRK 0x08 // Break Condition
// 0:no break condition, 1:break condition
#define LSR_RXF 0x10 // Receiver Data Register Condition
// 0:no data 1:has new byte coming in
#define LSR_TXE 0x20 // Transmitter Data Register Condition
// 0:not empty 1:empty
#define LSR_TMT 0x40 // Receiver Timeout Indication
// 0:not timeout 1:timeout
#define MSR_dCTS 0x01 // CTS* State Changed
// 0:no changed 1:changed
#define MSR_dDSR 0x02 // DSR* State Changed
// 0:no changed 1:changed
#define MSR_TRI 0x04 // Trailing edge of the ring-indicator.
// Indicate RI* pin changed from 0 to 1
// 0:RI* is high, 1:RI* pin changed
#define MSR_dCD 0x08 // CD* State Changed. Cleared by MCU Reading MSR
// 0:no changed 1:changed
#define MSR_LCTS 0x10 // During loopback mode, this reflects MCR[1]
// 0:CTS* is low, 1:CTS* is high
#define MSR_LDSR 0x20 // During loopback mode, this reflects MCR[0]
// 0:LDSR is high, 1:LDSR is low
#define MSR_LRI 0x40 // During loopback mode, this reflects MCR[2]
// 0:RI* is high, 1:RI* is low
#define MSR_LCD 0x80 // During loopback mode, this reflects MCR[3]
// 0:CD* is high, 1:CD* is low
// Baud Rate
#define BaudRate1200_DLL 0x01
#define BaudRate1200_DLH 0x03
#define BaudRate2400_DLL 0x81
#define BaudRate2400_DLH 0x01
#define BaudRate4800_DLL 0xC0
#define BaudRate4800_DLH 0x00
#define BaudRate7200_DLL 0x80
#define BaudRate7200_DLH 0x00
#define BaudRate9600_DLL 0x60
#define BaudRate9600_DLH 0x00
#define BaudRate14400_DLL 0x40
#define BaudRate14400_DLH 0x00
#define BaudRate19200_DLL 0x30
#define BaudRate19200_DLH 0x00
#define BaudRate38400_DLL 0x18
#define BaudRate38400_DLH 0x00
#define BaudRate57600_DLL 0x10
#define BaudRate57600_DLH 0x00
#define BaudRate115200_DLL 0x08
#define BaudRate115200_DLH 0x00
#define BaudRate230400_DLL 0x04
#define BaudRate230400_DLH 0x00
#define BaudRate460800_DLL 0x02
#define BaudRate460800_DLH 0x00
#define BaudRate921600_DLL 0x01
#define BaudRate921600_DLH 0x00
#define MASK_MIE 0x01 // Modem interrupt
#define MASK_SIE 0x02 // status interrupt
#define MASK_TRIE 0x04 // TxRx interrupt
#define VECINT_NO_INTERRUPT 0x00
#define VECINT_OUTPUT_ENDPOINT1 0x12
#define VECINT_OUTPUT_ENDPOINT2 0x14
#define VECINT_OUTPUT_ENDPOINT3 0x16
//#define VECINT_OUTPUT_ENDPOINT4 0x18
//#define VECINT_OUTPUT_ENDPOINT5 0x1A
//#define VECINT_OUTPUT_ENDPOINT6 0x1C
//#define VECINT_OUTPUT_ENDPOINT7 0x1E
#define VECINT_INPUT_ENDPOINT1 0x22
#define VECINT_INPUT_ENDPOINT2 0x24
#define VECINT_INPUT_ENDPOINT3 0x26
//#define VECINT_INPUT_ENDPOINT4 0x28
//#define VECINT_INPUT_ENDPOINT5 0x2A
//#define VECINT_INPUT_ENDPOINT6 0x2C
//#define VECINT_INPUT_ENDPOINT7 0x2E
#define VECINT_STPOW_PACKET_RECEIVED 0x30 // USBSTA
#define VECINT_SETUP_PACKET_RECEIVED 0x32 // USBSTA
#define VECINT_RESR_INTERRUPT 0x38 // USBSTA
#define VECINT_SUSR_INTERRUPT 0x3A // USBSTA
#define VECINT_RSTR_INTERRUPT 0x3C // USBSTA
#define VECINT_RWUP_INTERRUPT 0x3E // USBSTA
#define VECINT_I2C_RXF_INTERRUPT 0x40 // I2CSTA
#define VECINT_I2C_TXE_INTERRUPT 0x42 // I2CSTA
#define VECINT_INPUT_ENDPOINT0 0x44
#define VECINT_OUTPUT_ENDPOINT0 0x46
#define VECINT_UART1_STATUS_INTERRUPT 0x50
#define VECINT_UART1_MODEM_INTERRUPT 0x52
//#define VECINT_UART2_STATUS_INTERRUPT 0x54
//#define VECINT_UART2_MODEM_INTERRUPT 0x56
#define VECINT_UART1_RXF_INTERRUPT 0x60
#define VECINT_UART1_TXE_INTERRUPT 0x62
#define VECINT_DMA1_INTERRUPT 0x80
#define VECINT_DMA3_INTERRUPT 0x84
// Watchdog timer
#define WDCSR_WDT 0x01 // reset timer
//I2C Registers
#define I2CSTA_SWR 0x01 // Stop Write Enable
// 0:disable, 1:enable
#define I2CSTA_SRD 0x02 // Stop Read Enable
// 0:disable, 1:enable
#define I2CSTA_TIE 0x04 // I2C Transmitter Empty Interrupt Enable
// 0:disable, 1:enable
#define I2CSTA_TXE 0x08 // I2C Transmitter Empty
// 0:full, 1:empty
#define I2CSTA_400K 0x10 // I2C Speed Select
// 0:100kHz, 1:400kHz
#define I2CSTA_ERR 0x20 // Bus Error Condition
// 0:no bus error, 1:bus error
#define I2CSTA_RIE 0x40 // I2C Receiver Ready Interrupt Enable
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