start.s

此文件是硬盘自伺服刻录代码

; *******************************************************
; * Simple Little Operating System - SLOS
; *******************************************************

; ****************************************************************************
; *
; * Module     : start.s
; * Project	: SLOS
; * Version	: 0.09
; * Originator	: Andrew N. Sloss
; * History    :
; * 
; * 16th July 2003 Andrew N. Sloss
; * - added header information
; *
; ****************************************************************************

; ****************************************************************************
; * IMPORT 
; ****************************************************************************

;     IMPORT    coreInitialize
     IMPORT    OS_CPU_UNDEFINED
     IMPORT    OS_CPU_SWI
     IMPORT    OS_CPU_PREFETCHABORT
     IMPORT    OS_CPU_DATAABORT
     IMPORT    OS_CPU_RESERVED
     IMPORT    OS_CPU_IRQ_ISR
     IMPORT    OS_CPU_FIQ_ISR
     IMPORT    C_MAIN
;     IMPORT    PCB_Table
     
     


     AREA ENTRYSLOS,CODE,READONLY

; ****************************************************************************
; * CODE 
; ****************************************************************************

     ENTRY
 
; ----------------------------------------------------
; table offset .......... 
; 00 - Reset
; 04 - Undefined instructions
; 08 - SWI instructions
; 0C - prefetch abort
; 10 - Data abort
; 14 - Reserved
; 18 - IRQ interrupts
; 1C - FIQ interrupts
; ----------------------------------------------------

     LDR     pc,vectorReset
     LDR     pc,vectorUndefined    
     LDR     pc,vectorSWI
     LDR     pc,vectorPrefetchAbort
     LDR     pc,vectorDataAbort
     LDR     pc,vectorReserved
     LDR     pc,vectorIRQ
     LDR     pc,vectorFIQ

; -- Useful address to the PCB tables ------------------ 

;ptrPCBTable         DCD  PCB_Table

; -- Kernel Jump table ------------------------------ 

vectorReset         DCD     coreInitialize
vectorUndefined     DCD     OS_CPU_UNDEFINED
vectorSWI           DCD     OS_CPU_SWI
vectorPrefetchAbort DCD     OS_CPU_PREFETCHABORT
vectorDataAbort     DCD     OS_CPU_DATAABORT
vectorReserved      DCD     OS_CPU_RESERVED
vectorIRQ           DCD     OS_CPU_IRQ_ISR
vectorFIQ           DCD     OS_CPU_FIQ_ISR


;-----Initialize----------------------------------------

coreInitialize
; ------------------------------------------------
; Setup stacks for SVC,IRQ,SYS&USER 
; Mode = SVC 
; ------------------------------------------------

     MOV     sp,#0x28000           ; initializing sp to TopOfMemory
     MSR     CPSR_c,#0xc0|0x1f
     MOV     sp,#0x26000           ; SYS/User Stack = 0x40000
     MSR     CPSR_c,#0xc0|0x12
     MOV     sp,#0x24000            ; IRQ Stack = 0x9000
     MSR     CPSR_c,#0xc0|0x13
     
;--------------------------------------------------
;
;give control power
;
;---------------------------------------------------
     LDR     lr,=C_MAIN
     MOV     pc,lr                ; call C_MAIN

     END