define.h

此文件是硬盘自伺服刻录代码

// **************************************
// register definition and default value
// register is little endian
// **************************************

// register for test
/*
#define D0SSMF *(volatile unsigned *)1000251E		// bit 0, send SSMF on D0 in no_NRZ mode for diagnostic
#define SSM *(volatile unsigned *)10002568			// channel servo sync mark
#define NRZ_DIAG *(volatile unsigned *)100025B6		// bit 6&7 = 10 
#define TST_PORT_H *(volatile unsigned *)1000A820		// SGATE,NRZ
#define TST_PORT_L *(volatile unsigned *)1000A822		// FIQ,IRQ,SBD,SRVINDEX,SRVSYNC
*/ // channel



// CPU
#define CPU_WARM_RST *(volatile unsigned short *)0x10008004
#define INT_CTL *(volatile unsigned short *)0x10008006
#define TO_EN *(volatile unsigned short *)0x1000800c



// reset
#define SOFT_RST *(volatile unsigned char *)0x10002402
//#define SOFT_RST_Mask 0x80							// a 1 to 0 toggle
// analog calibration
#define LFG_N *(volatile unsigned *)0x1000250A  	// bit 4:0
#define ACAL *(volatile unsigned *)0x100025F0
#define TBG_CAL *(volatile unsigned *)0x1000240A


// power and clk manage
#define PWR_CTL *(volatile unsigned short *)0x1000A806
#define CLK_DVD0 *(volatile unsigned short *)0x1000A802


// servo clock frequency
// Fs=Fr*(FS_NF+2)*(SFG_NF+2)/(SFG_NS+2)
// 4.69 < Fr * (FS_NF+2)/(SFG_NS+2)  < 6.2
// Fsync = (FS_NF+2)*Fref, Fsync should be close to 600MHz
#define FS_NF *(volatile unsigned char *)0x10002580		// all 8 bits	// F0
#define SFG_NF *(volatile unsigned char *)0x1000258E		// lower 7 bits	// 87
#define SFG_NS *(volatile unsigned char *)0x1000258C						// 66
//#define CLK_Mask 0x7F
#define SG_EXT_EN *(volatile unsigned char *)0x10002516
#define SRV_CLK_SEL *(volatile unsigned *)0x1000A804				// 16 bits, 0xA424, servo clk from OSC 
// #define SRV_CLK_SEL_Mask 0x0018									// bit 3&4, osc or channel?
#define SRV_CLK_EN *(volatile unsigned *)0x1000A806
#define SRV_CFG5 *(volatile unsigned *)0x1000251A					// 0x50 (meanwhile, PES is in Mag and Phase form, also, 8-bit sync mark)
//#define SRV_CLK_CTL_Mask 0x04										// bit 2, 1 for SVRCLK all the time



// servo pattern format
// RRO is ignored although default register values makes RRO exist. delay the disassertion of SG to accomodate RRO field
// encode format
#define ENC_FMT *(volatile unsigned char *)0x10002518			// 0x00, manchester encode for all
// channel gray code length
#define GC_LEN_CNL *(volatile unsigned char *)0x100025AC			// 0x1F
// SIM SAM format
#define SIM *(volatile unsigned char *)0x100025A8				// 0x14
#define SAM *(volatile unsigned char *)0x100025AA				// 0x27
// Burst number
#define BG_N *(volatile unsigned char *)0x100025DA				// 0x03, #Burst=3
// Burst GAP
#define BG_GAP *(volatile unsigned char *)0x100025C6				// 0x43, gap DE=4
#define BG_GAP_EN *(volatile unsigned char *)0x100025DE			// 0x40, disable BC, enable DE, RRO_LEN=0
// GCAL and RRO1/2
#define S_CFG1 *(volatile unsigned char *)0x10002512				// 0x01, disable RRO1/2 and GCAL



// servo data
// controller servo data storage and process cfg, 
//	i.e: gray code number, burst length, RRO length, and GC decode start point
#define SRV_DATA_CFG *(volatile unsigned *)0x100026A8		// 0xDE01
// controller gray code 
// #define GC_DATA_H *(volatile unsigned *)0x100026B0		
// #define GC_DATA_L *(volatile unsigned *)0x100026B2
// controller fromatted gray code , good!!!  in this case, SSN is extracted
//     only bits [7:23] are valid!!!
//  we need to know the base for track 0 !!!
#define GC_DATA_H *(volatile unsigned *)0x100026DE
#define GC_DATA_L *(volatile unsigned *)0x100026DC
// controller formatted servo burst data, good!!!
#define SRV_B_A *(volatile unsigned *)0x100026B4	// continuous 4
#define SRV_B_B *(volatile unsigned *)0x100026B6
#define SRV_B_C *(volatile unsigned *)0x100026B8
#define SRV_B_D *(volatile unsigned *)0x100026BA
// servo formatted sector number, good !!!
#define SSN *(volatile unsigned *)0x100026D8 				// formatted SSN



// servo pattern timing
// ACQ
#define S_ACQ_DLY *(volatile unsigned char *)0x100025C8			// 0x04
#define S_ACQ1 *(volatile unsigned char *)0x100025CA			// 0x09, LFSM_MASK=0, ACQ1LEN=9
#define S_ACQ2 *(volatile unsigned char *)0x100025CC			// 0x10, ACQ2LEN=16
#define S_ACQ3 *(volatile unsigned char *)0x100025CE			// 0x00, ACQ3LEN=0
// !!!! NEED OPTIMIZATION !!!! , TOO LARGE
#define S_SMDTMO *(volatile unsigned char *)0x100025D2		// 0x30, CHANGE TO 0x22
// !! TRY CHANGE BG_DLY1 TO 0X13
#define BG_DLY1 *(volatile unsigned char *)0x100025D4		// 0x11, TIME = 20
#define BG_DLY2 *(volatile unsigned char *)0x100025D6		// 0x10, TIME = 18, WHEN ERROR OCCURS
// BUSRT GAP AND LENGTH
#define BG_INTEGRATION *(volatile unsigned char *)0x100025D8		// 0x37, GAP=4, LEN=8
// SG_EXT_TMO
#define SG_EXT_TMO *(volatile unsigned char *)0x100025EE			// 0x05



// test[7:0] output
#define TST *(volatile unsigned *)0x1000A820			// 0x05


// servo status(read only)
#define SSMF_STATUS *(volatile unsigned *)0x10002568		// SIM, SAM, SSMF, SMERR


// servo interface
#define SRV_CFG0 *(volatile unsigned char *)0x10002510			// 0x08, NRZ mode
#define SRV_CFG1 *(volatile unsigned char *)0x10002512			// 0x01
#define SRV_CFG2 *(volatile unsigned char *)0x10002514			// 0x70, transfer Qs.
#define SRV_CFG3 *(volatile unsigned char *)0x10002516			// 0x9E, enable SAM/SIM detect, enable SG_EXT_EN
#define SRV_CFG4 *(volatile unsigned char *)0x10002518			// 0x00
// SRV_CFG5 is defined in clk block, and set to 0x50
#define SRV_CFG6 *(volatile unsigned char *)0x1000251C			// 0x00, tolerance is set to 0
#define SRV_CFG7 *(volatile unsigned char *)0x1000251E			// 0x10, enable manche code detector
#define PES_TX_MODE *(volatile unsigned char *)0x100025E0		// 0x00, only send PES Mag
#define PES_Shift *(volatile unsigned char *)0x100025E4			// 0x00, no PES sign, don't shift PES vlaue


// servo status
#define WCS_ADDR *(volatile unsigned *)0x10002684
#define WCS_VALUE *(volatile unsigned *)0x10002688
#define WCS_COUNT *(volatile unsigned *)0x10002686				// 16 bits
#define SSM *(volatile unsigned char *)0x10002568
//WCS set registor
#define WCS_SSICV *(volatile unsigned *)0x10002688
#define WCS_ServoStatus *(volatile unsigned *)0x1000268c
//#define the Write pattern!
#define WWCS_BASE (volatile unsigned *)0x10002C80
 





// preamp interface
// 0x10002530 --  2536

// **************************************
// WCS code
// **************************************
#define WCS_BASE (volatile unsigned *)0x10002600	// WCS RAM base address

#define SQ_CTL *(volatile unsigned *)0x10002680		// sequencer control
#define SRV_SYNC_TO *(volatile unsigned *)0x1000269C		// sequencer control

// WCS command
unsigned RAMData[30]={
// cmd format:  cnt_4, condition_branch2, action_2												// debug

	// 1. accquire mode
	// all signal down for 10sclks, except for INT
	0x00020420,
//    x00020400,
	// to consist with example only
	0x00020420,	
//    0x00020400,	
	// assert SGATE and start-up mode for longer time, 13us, half the servo block
	0x01040323,		// old 628 	: 0x0274	
//    0x01040303,													// a0 -- ffff
	// SAM found. old code, maintain SG and start-up mode for 6sclk
	0x00060423,		// once find, loop infinitely												// 0xffff1d20
	// counter modified to 6.7-0.32us
	// ...do not assert interrupt
	0x00800423,		// old 128	: 0x0080
//    0x00800403,
	// drop SG and start-up mode, delay 131.7us for next servo
	0x0a4a0420,		// old 4829	: 0x12DD
//    0x0a4a0400,	
	// assert SG and start-up mode, look for Sync mark within 5us (or 65 dibits)
	0x00640323,		// 184	: 00B8
//    0x00640303,	
	// maintain SG and drop start-up mode
	0x00080422,
//    0x00080402,
	// maintain SG till end of wedge, do not assert interrupt
	0x00860422,
//    0x00860402,
	// drop SG and delay
	0x0a4a0420,
//    0x0a4a0400,
	
	// 2. track mode
	// look for sync within 65 dibits with SG high
	0x00847B22,		// 184 0f 03   647b22
	// maintain SG till wedge end, 670 slks
	0x00800432,																					// SSN+1 works how long?
	// drop SG and assert interrupt for 600ns
	0x000C0400,		// 126
	// branch to switch head ?
	0x0001BA28,		// 1 17 02 old value 0001ba20																	// 0x0001BA0A
	// disassert interrupt and delay
	0x0a305528,    //a49       old value 0a305520
	
	// 3. recover mode 
	// assert SG for 5.3us, so totally 10.3us
//	0x006a0422,
    0x00847B02,	
	// drop SG and delay
	0x0a4a0420,
	// detect again
	0x00649B22,
	// yes, maintain SG till wedge end, and jump
	0x00866522,
	// timeout, maintain SG for 5.3us
	0x006a0422,
	// drop SG and delay
	0x0a4a0420,
	// assert SG and detect again
	0x00640322,
	// yes, maintain SG till wedge end, and jump
	0x00866522,
	
	// 4. switch head
	0x02580420,		// 3000 for safey
	// strange 1 sclk delay
	0x00010420,
	// look for sync
	0x00647B22,
	// yes, SG 670us
	0x0006042A,		// 70
	0x0080042A,		// 600
	// delay
	0x0a49CA20,
	0x0001512A
	
	};
//The Serial Interface Control 	
#define SerInface_0 		*(volatile unsigned char *)0x10002400
#define SerInface_1 		*(volatile unsigned char *)0x10002402
#define SerInface_2 		*(volatile unsigned char *)0x10002404
#define SerInface_3 		*(volatile unsigned char *)0x10002406
#define ErroRecovery 		*(volatile unsigned char *)0x10002408
//TimeBase Setting
#define TimeBaseGC  		*(volatile unsigned char *)0x1000240A
#define TimeBaseGSD  		*(volatile unsigned char *)0x1000240C
#define TimeBaseGFD  		*(volatile unsigned char *)0x1000240e
//The Channel Statistics Measurement registors setting
#define ChanStatisMeasure_0 *(volatile unsigned char *)0x10002410
#define ChanStatisMeasure_1 *(volatile unsigned char *)0x10002412
#define ChanStatisMeasure_2 *(volatile unsigned char *)0x10002414
#define ChanStatisMeasure_3 *(volatile unsigned char *)0x10002416
#define ChanStatisMeasure_4 *(volatile unsigned char *)0x10002418
#define ChanStatisMeasure_5 *(volatile unsigned char *)0x1000241A
#define ChanStatisMeasure_6 *(volatile unsigned char *)0x1000241C
#define ChanStatisMeasure_7 *(volatile unsigned char *)0x1000241E
#define ChanStatisMeasure_8 *(volatile unsigned char *)0x10002420
#define ChanStatisMeasure_9 *(volatile unsigned char *)0x10002422
#define ChanStatisMeasure_10 *(volatile unsigned char *)0x10002424
//VGA Registor Control
#define VGARegistor_0  		*(volatile unsigned char *)0x10002426
#define VGARegistor_1  		*(volatile unsigned char *)0x10002428
#define VGARegistor_2  		*(volatile unsigned char *)0x1000242a
#define VGARegistor_3  		*(volatile unsigned char *)0x1000242c
#define VGARegistor_4  		*(volatile unsigned char *)0x1000242e
//Define Asemmetry Correction control
#define AsemmetryCoren_0  	*(volatile unsigned char *)0x10002430
#define AsemmetryCoren_1  	*(volatile unsigned char *)0x10002432
#define AsemmetryCoren_2  	*(volatile unsigned char *)0x10002434
//Data Mode CTF controller 
#define DataCTFControl_0  	*(volatile unsigned char *)0x10002436
#define DataCTFControl_1  	*(volatile unsigned char *)0x10002438
#define DataCTFControl_2  	*(volatile unsigned char *)0x1000243a
#define DataCTFControl_3  	*(volatile unsigned char *)0x1000243c
#define DataCTFControl_4  	*(volatile unsigned char *)0x1000243e
//Data Mode FIR coef setting
#define DataFIRCoef_0   	*(volatile unsigned char *)0x10002440
#define DataFIRCoef_1   	*(volatile unsigned char *)0x10002442