run

嵌入式操作系统的基本输入输出程序

#!/bin/csh

ncverilog							\
		+define+TEST_BENCH				\
								\
		../verilog/core/alu.v				\
		../verilog/core/presclr_wdt.v			\
		../verilog/core/risc_core.v			\
		../verilog/core/primitives.v			\
		../verilog/core/register_file.v			\
		../verilog/core/risc_core_top.v			\
		../verilog/testbench/prog_mem.v			\
		../verilog/testbench/test.v			\
									\
		../../generic_memories/rtl/verilog/generic_spram.v	\
		../../generic_memories/rtl/verilog/generic_dpram.v