advioreg.c

pc机上经由pci连接的ata和atapi设备驱动

//                            using an LBA sector address.
//
//*************************************************************

int reg_pio_data_out_lba48( int cmd,
                            unsigned int fr, unsigned int sc,
                            unsigned long lbahi, unsigned long lbalo,
                            unsigned int seg, unsigned int off,
                            long numSect, int multiCnt )

{

   // Reset error return data.

   sub_zero_return_data();
   ADP->flg = TRC_FLAG_ATA;
   ADP->ct  = TRC_TYPE_APDO;
   ADP->cmd = cmd;
   ADP->fr1 = fr;
   ADP->sc1 = sc;
   ADP->dh1 = CB_DH_LBA | ADP->devBit;
   // ADP->dc1 = 0x00;     // see sub_setup_command()
   ADP->lbaSize = LBA48;
   ADP->lbaHigh1 = lbahi;
   ADP->lbaLow1 = lbalo;

   // only Write Multiple Ext uses multCnt
   if ( cmd != CMD_WRITE_MULTIPLE_EXT )
      multiCnt = 1;

   ADP->ns  = numSect;
   ADP->mc  = multiCnt;

   return exec_pio_data_out_cmd( seg, off, numSect, multiCnt );
}

#if ADVIO_INCL_ATAPI_PIO

//*************************************************************
//
// reg_packet() - Execute an ATAPI Packet (A0H) command.
//
// See ATA-4 Section 9.10, Figure 14.
//
//*************************************************************

int reg_packet(
                unsigned int cpbc,
                unsigned int cpseg, unsigned int cpoff,
                int dir,
                long dpbc,
                unsigned int dpseg, unsigned int dpoff,
                unsigned long lba )

{
   unsigned char status;
   unsigned char reason;
   unsigned char lowCyl;
   unsigned char highCyl;
   unsigned int byteCnt;
   long wordCnt;
   int ndx;
   unsigned long dpaddr;
   unsigned char far * cfp;
   int prevFailBit7 = 0;

   // mark start of PI cmd in low level trace

   trc_llt( 0, 0, TRC_LLT_S_PI );

   // reset Bus Master Error bit

   sub_writeBusMstrStatus( BM_SR_MASK_ERR );

   // Make sure the command packet size is either 12 or 16
   // and save the command packet size and data.

   cpbc = cpbc < 12 ? 12 : cpbc;
   cpbc = cpbc > 12 ? 16 : cpbc;

   // Setup current command information.

   sub_zero_return_data();
   ADP->flg = TRC_FLAG_ATAPI;
   ADP->ct  = dir ? TRC_TYPE_PPDO : TRC_TYPE_PPDI;
   ADP->cmd = CMD_PACKET;
   ADP->fr1 = ADP->reg_atapi_reg_fr;
   ADP->sc1 = ADP->reg_atapi_reg_sc;
   ADP->sn1 = ADP->reg_atapi_reg_sn;
   ADP->cl1 = (unsigned char) ( dpbc & 0x00ff );
   ADP->ch1 = ( unsigned char) ( ( dpbc & 0xff00 ) >> 8 );
   ADP->dh1 = ADP->devBit | ( ADP->reg_atapi_reg_dh & 0x0f );
   // ADP->dc1 = 0x00;     // see sub_setup_command()
   ADP->lbaSize = LBA32;
   ADP->lbaLow1 = lba;
   ADP->lbaHigh1 = 0L;
   ADP->reg_atapi_cp_size = cpbc;
   cfp = MK_FP( cpseg, cpoff );
   for ( ndx = 0; ndx < cpbc; ndx ++ )
   {
      ADP->reg_atapi_cp_data[ndx] = * cfp;
      cfp ++ ;
   }

   // Zero the alternate ATAPI register data.

   ADP->reg_atapi_reg_fr = 0;
   ADP->reg_atapi_reg_sc = 0;
   ADP->reg_atapi_reg_sn = 0;
   ADP->reg_atapi_reg_dh = 0;

   // Set command time out.

   tmr_set_timeout();

   // Select the drive - call the sub_select function.
   // Quit now if this fails.

   if ( sub_select() )
   {
      sub_trace_command();
      trc_llt( 0, 0, TRC_LLT_E_PI );
      return 1;
   }

   // Set up all the registers except the command register.

   sub_setup_command();

   // Start the command by setting the Command register.  The drive
   // should immediately set BUSY status.

   pio_outbyte( CB_CMD, CMD_PACKET );

   // Waste some time by reading the alternate status a few times.
   // This gives the drive time to set BUSY in the status register on
   // really fast systems.  If we don't do this, a slow drive on a fast
   // system may not set BUSY fast enough and we would think it had
   // completed the command when it really had not even started the
   // command yet.

   DELAY400NS;

   // Command packet transfer...
   // Check for protocol failures,
   // the device should have BSY=1 or
   // if BSY=0 then either DRQ=1 or CHK=1.

   status = pio_inbyte( CB_ASTAT );
   if ( status & CB_STAT_BSY )
   {
      // BSY=1 is OK
   }
   else
   {
      if ( status & ( CB_STAT_DRQ | CB_STAT_ERR ) )
      {
         // BSY=0 and DRQ=1 is OK
         // BSY=0 and ERR=1 is OK
      }
      else
      {
         ADP->failbits |= FAILBIT0;  // not OK
      }
   }

   // Command packet transfer...
   // Poll Alternate Status for BSY=0.

   trc_llt( 0, 0, TRC_LLT_PNBSY );
   while ( 1 )
   {
      status = pio_inbyte( CB_ASTAT );       // poll for not busy
      if ( ( status & CB_STAT_BSY ) == 0 )
         break;
      if ( tmr_chk_timeout() )               // time out yet ?
      {
         trc_llt( 0, 0, TRC_LLT_TOUT );      // yes
         ADP->to = 1;
         ADP->ec = 51;
         trc_llt( 0, ADP->ec, TRC_LLT_ERROR );
         dir = -1;   // command done
         break;
      }
   }

   // Command packet transfer...
   // If no error, transfer the command packet.

   if ( ADP->ec == 0 )
   {

      // Command packet transfer...
      // Read the primary status register and the other ATAPI registers.

      status = pio_inbyte( CB_STAT );
      reason = pio_inbyte( CB_SC );
      lowCyl = pio_inbyte( CB_CL );
      highCyl = pio_inbyte( CB_CH );

      // Command packet transfer...
      // check status: must have BSY=0, DRQ=1 now

      if (    ( status & ( CB_STAT_BSY | CB_STAT_DRQ | CB_STAT_ERR ) )
           != CB_STAT_DRQ
         )
      {
         ADP->ec = 52;
         trc_llt( 0, ADP->ec, TRC_LLT_ERROR );
         dir = -1;   // command done
      }
      else
      {
         // Command packet transfer...
         // Check for protocol failures...
         // check: C/nD=1, IO=0.

         if ( ( reason &  ( CB_SC_P_TAG | CB_SC_P_REL | CB_SC_P_IO ) )
              || ( ! ( reason &  CB_SC_P_CD ) )
            )
            ADP->failbits |= FAILBIT2;
         if (    ( lowCyl != ADP->cl1 )
              || ( highCyl != ADP->ch1 ) )
            ADP->failbits |= FAILBIT3;

         // Command packet transfer...
         // trace cdb byte 0,
         // xfer the command packet (the cdb)

         trc_llt( 0, * (unsigned char far *) MK_FP( cpseg, cpoff ), TRC_LLT_P_CMD );
         pio_drq_block_out( CB_DATA, cpseg, cpoff, cpbc >> 1 );

         DELAY400NS;    // delay so device can get the status updated
      }
   }

   // Data transfer loop...
   // If there is no error, enter the data transfer loop.
   // First adjust the I/O buffer address so we are able to
   // transfer large amounts of data (more than 64K).

   dpaddr = dpseg;
   dpaddr = dpaddr << 4;
   dpaddr = dpaddr + dpoff;

   while ( ADP->ec == 0 )
   {
      // Data transfer loop...
      // Poll for not BUSY -or- wait for time out.

      reg_poll_not_busy( 54 );

      // Data transfer loop...
      // If there was a time out error, exit the data transfer loop.

      if ( ADP->ec )
      {
         dir = -1;   // command done
         break;
      }

      // Data transfer loop...
      // Read the primary status register.

      status = pio_inbyte( CB_STAT );
      reason = pio_inbyte( CB_SC );
      lowCyl = pio_inbyte( CB_CL );
      highCyl = pio_inbyte( CB_CH );

      // Data transfer loop...
      // Exit the read data loop if the device indicates this
      // is the end of the command.

      if ( ( status & ( CB_STAT_BSY | CB_STAT_DRQ ) ) == 0 )
      {
         dir = -1;   // command done
         break;
      }

      // Data transfer loop...
      // The device must want to transfer data...
      // check status: must have BSY=0, DRQ=1 now.

      if ( ( status & ( CB_STAT_BSY | CB_STAT_DRQ ) ) != CB_STAT_DRQ )
      {
         ADP->ec = 55;
         trc_llt( 0, ADP->ec, TRC_LLT_ERROR );
         dir = -1;   // command done
         break;
      }
      else
      {
         // Data transfer loop...
         // Check for protocol failures...
         // check: C/nD=0, IO=1 (read) or IO=0 (write).

         if ( ( reason &  ( CB_SC_P_TAG | CB_SC_P_REL ) )
              || ( reason &  CB_SC_P_CD )
            )
            ADP->failbits |= FAILBIT4;
         if ( ( reason & CB_SC_P_IO ) && dir )
            ADP->failbits |= FAILBIT5;
      }

      // Data transfer loop...
      // get the byte count, check for zero...

      byteCnt = ( highCyl << 8 ) | lowCyl;
      if ( byteCnt < 1 )
      {
         ADP->ec = 59;
         trc_llt( 0, ADP->ec, TRC_LLT_ERROR );
         dir = -1;   // command done
         break;
      }

      // Data transfer loop...
      // and check protocol failures...

      if ( byteCnt > dpbc )
         ADP->failbits |= FAILBIT6;
      ADP->failbits |= prevFailBit7;
      prevFailBit7 = 0;
      if ( byteCnt & 0x0001 )
         prevFailBit7 = FAILBIT7;

      // Data transfer loop...
      // quit if buffer overrun.

      if ( ( ADP->totalBytesXfer + byteCnt ) > ADP->reg_buffer_size )
      {
         ADP->ec = 61;
         trc_llt( 0, ADP->ec, TRC_LLT_ERROR );
         dir = -1;   // command done
         break;
      }

      // increment number of DRQ packets

      ADP->drqPackets ++ ;

      // Data transfer loop...
      // transfer the data and update the i/o buffer address
      // and the number of bytes transfered.

      wordCnt = ( byteCnt >> 1 ) + ( byteCnt & 0x0001 );
      ADP->totalBytesXfer += ( wordCnt << 1 );
      dpseg = (unsigned int) ( dpaddr >> 4 );
      dpoff = (unsigned int) ( dpaddr & 0x0000000fL );
      if ( dir )
         pio_drq_block_out( CB_DATA, dpseg, dpoff, wordCnt );
      else
         pio_drq_block_in( CB_DATA, dpseg, dpoff, wordCnt );
      dpaddr = dpaddr + byteCnt;

      DELAY400NS;    // delay so device can get the status updated
   }

   // End of command...
   // Poll for BSY=0,
   // but don't do this if there was any error or if this
   // was a commmand that did not transfer data.

   if ( ( ADP->ec == 0 ) && ( dir >= 0 ) )
   {
      reg_poll_not_busy( 57 );
   }

   // Final status check, only if no previous error.

   if ( ADP->ec == 0 )
   {
      // Final status check...
      // Read the primary status register and other regs.

      status = pio_inbyte( CB_STAT );
      reason = pio_inbyte( CB_SC );
      lowCyl = pio_inbyte( CB_CL );
      highCyl = pio_inbyte( CB_CH );

      // Final status check...
      // check for any error.

      if ( status & ( CB_STAT_BSY | CB_STAT_DRQ | CB_STAT_ERR ) )
      {
         ADP->ec = 58;
         trc_llt( 0, ADP->ec, TRC_LLT_ERROR );
      }
   }

   // Final status check...
   // Check for protocol failures...
   // check: C/nD=1, IO=1.

   if ( ( reason & ( CB_SC_P_TAG | CB_SC_P_REL ) )
        || ( ! ( reason & CB_SC_P_IO ) )
        || ( ! ( reason & CB_SC_P_CD ) )
      )
      ADP->failbits |= FAILBIT8;

   // Done...
   // Read the output registers and trace the command.

   if ( ! ADP->totalBytesXfer )
      ADP->ct = TRC_TYPE_PND;
   sub_trace_command();

   // Final status check
   // BMCR/BMIDE Error=1?

   if ( sub_readBusMstrStatus() & BM_SR_MASK_ERR )
   {
      ADP->ec = 78;                  // yes
      trc_llt( 0, ADP->ec, TRC_LLT_ERROR );
   }

   // mark end of PI cmd in low level trace

   trc_llt( 0, 0, TRC_LLT_E_PI );

   // All done.  The return values of this function are described in
   // ADVIO.H.

   if ( ADP->ec )
      return 1;
   return 0;
}

#endif

// end advioreg.c