📄 rt2570.h
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typedef union _CSR15_STRUC { struct { ULONG Cfp:1; // CFP period ULONG Atimw:1; // Atim window period ULONG BeaconSent:1; // Beacon sent ULONG Rsvd:29; } field; ULONG word;} CSR15_STRUC, *PCSR15_STRUC;//// CSR18: IFS Timer register 0//typedef union _CSR18_STRUC { struct { ULONG SIFS:16; // SIFS, default is 10 TU ULONG PIFS:16; // PIFS, default is 30 TU } field; ULONG word;} CSR18_STRUC, *PCSR18_STRUC;//// CSR19: IFS Timer register 1//typedef union _CSR19_STRUC { struct { ULONG DIFS:16; // DIFS, default is 50 TU ULONG EIFS:16; // EIFS, default is 364 TU } field; ULONG word;} CSR19_STRUC, *PCSR19_STRUC;//// MAC_CSR18: Wakeup timer register//typedef union _MAC_CSR18_STRUC { struct { USHORT DelayAfterBcn:8; // Delay after Tbcn expired in units of 1/16 TU USHORT NumBcnBeforeWakeup:7; // Number of beacon before wakeup USHORT AutoWake:1; // Enable auto wakeup / sleep mechanism } field; USHORT value;} MAC_CSR18_STRUC, *PMAC_CSR18_STRUC;#if 0//RT2560//// CSR20: Wakeup timer register//typedef union _CSR20_STRUC { struct { ULONG DelayAfterBcn:16; // Delay after Tbcn expired in units of 1/16 TU ULONG NumBcnBeforeWakeup:8; // Number of beacon before wakeup ULONG AutoWake:1; // Enable auto wakeup / sleep mechanism ULONG Rsvd:7; } field; ULONG word;} CSR20_STRUC, *PCSR20_STRUC;#endif//// CSR21: EEPROM control register//typedef union _CSR21_STRUC { struct { ULONG Reload:1; // Reload EEPROM content, write one to reload, self-cleared. ULONG EepromSK:1; ULONG EepromCS:1; ULONG EepromDI:1; ULONG EepromDO:1; ULONG Type:1; // 1: 93C46, 0:93C66 ULONG Rsvd:26; } field; ULONG word;} CSR21_STRUC, *PCSR21_STRUC;//// CSR22: CFP control register//typedef union _CSR22_STRUC { struct { ULONG CfpDurRemain:16; // CFP duration remain, in units of TU ULONG ReloadCfpDurRemain:1; // Reload CFP duration remain, write one to reload, self-cleared ULONG Rsvd:15; } field; ULONG word;} CSR22_STRUC, *PCSR22_STRUC;// =================================================================================// TX / RX Registers// =================================================================================//// TXCSR0 <0x0060> : TX Control Register //typedef union _TXCSR0_STRUC { struct { ULONG KickTx:1; // Kick Tx ring ULONG KickAtim:1; // Kick ATIM ring ULONG KickPrio:1; // Kick priority ring ULONG Abort:1; // Abort all transmit related ring operation ULONG Rsvd:28; } field; ULONG word;} TXCSR0_STRUC, *PTXCSR0_STRUC;//// TXRX_CSR0: Security control register//typedef union _TXRX_CSR0_STRUC { struct { USHORT Algorithm:3; USHORT IVOffset:6; USHORT KeyID:4; USHORT Rsvd:3; } field; USHORT value;} TXRX_CSR0_STRUC, *PTXRX_CSR0_STRUC;//// TXCSR1 <0x0064> : TX Configuration Register//typedef union _TXCSR1_STRUC { struct { ULONG AckTimeOut:9; // Ack timeout, default = SIFS + 2*SLOT_ACKtime @ 1Mbps ULONG AckConsumeTime:9; // ACK consume time, default = SIFS + ACKtime @ 1Mbps ULONG TsFOffset:6; // Insert Tsf offset ULONG AutoResponder:1; // enable auto responder which include ACK & CTS ULONG Reserved:7; } field; ULONG word;} TXCSR1_STRUC, *PTXCSR1_STRUC;//// TXCSR2: Tx descriptor configuration register//typedef union _TXCSR2_STRUC { struct { ULONG TxDSize:8; // Tx descriptor size, default is 32 ULONG NumTxD:8; // Number of TxD in ring ULONG NumAtimD:8; // Number of AtimD in ring ULONG NumPrioD:8; // Number of PriorityD in ring } field; ULONG word;} TXCSR2_STRUC, *PTXCSR2_STRUC;//// TXCSR7: Auto responder control register//typedef union _TXCSR7_STRUC { struct { ULONG ARPowerManage:1; // Auto responder power management bit ULONG Rsvd:31; } field; ULONG word;} TXCSR7_STRUC, *PTXCSR7_STRUC;//// RXCSR0 <0x0080> : RX Control Register//typedef union _RXCSR0_STRUC { struct { ULONG DisableRx:1; // Disable Rx engine ULONG DropCRC:1; // Drop CRC error ULONG DropPhysical:1; // Drop physical error ULONG DropControl:1; // Drop control frame ULONG DropNotToMe:1; // Drop not to me unicast frame ULONG DropToDs:1; // Drop fram ToDs bit is true ULONG DropVersionErr:1; // Drop version error frame ULONG PassCRC:1; // Pass all receive packet to host with CRC attached ULONG Reserved:24; } field; ULONG word;} RXCSR0_STRUC, *PRXCSR0_STRUC;//// RXCSR1: RX descriptor configuration register//typedef union _RXCSR1_STRUC { struct { ULONG RxDSize:8; // Rx descriptor size, default is 32B. ULONG NumRxD:8; // Number of RxD in ring. ULONG Rsvd:16; } field; ULONG word;} RXCSR1_STRUC, *PRXCSR1_STRUC;//// RXCSR3: BBP ID register for Rx operation//typedef union _RXCSR3_STRUC { struct { ULONG IdBbp0:7; // BBP register 0 ID ULONG ValidBbp0:1; // BBP register 0 ID is valid or not ULONG IdBbp1:7; // BBP register 1 ID ULONG ValidBbp1:1; // BBP register 1 ID is valid or not ULONG IdBbp2:7; // BBP register 2 ID ULONG ValidBbp2:1; // BBP register 2 ID is valid or not ULONG IdBbp3:7; // BBP register 3 ID ULONG ValidBbp3:1; // BBP register 3 ID is valid or not } field; ULONG word;} RXCSR3_STRUC, *PRXCSR3_STRUC;//// RXCSR4: BBP ID register for Rx operation//typedef union _RXCSR4_STRUC { struct { ULONG IdBbp4:7; // BBP register 4 ID ULONG ValidBbp4:1; // BBP register 4 ID is valid or not ULONG IdBbp5:7; // BBP register 5 ID ULONG ValidBbp5:1; // BBP register 5 ID is valid or not ULONG Rsvd:16; } field; ULONG word;} RXCSR4_STRUC, *PRXCSR4_STRUC;//// ARCSR0: Auto Responder PLCP value register 0//typedef union _ARCSR0_STRUC { struct { ULONG ArBbpData0:8; // Auto responder BBP register 0 data ULONG ArBbpId0:8; // Auto responder BBP register 0 Id ULONG ArBbpData1:8; // Auto responder BBP register 1 data ULONG ArBbpId1:8; // Auto responder BBP register 1 Id } field; ULONG word;} ARCSR0_STRUC, *PARCSR0_STRUC;//// ARCSR0: Auto Responder PLCP value register 1//typedef union _ARCSR1_STRUC { struct { ULONG ArBbpData2:8; // Auto responder BBP register 2 data ULONG ArBbpId2:8; // Auto responder BBP register 2 Id ULONG ArBbpData3:8; // Auto responder BBP register 3 data ULONG ArBbpId3:8; // Auto responder BBP register 3 Id } field; ULONG word;} ARCSR1_STRUC, *PARCSR1_STRUC;// =================================================================================// Miscellaneous Registers// =================================================================================//// PCISR: PCI control register//typedef union _PCICSR_STRUC { struct { ULONG BigEndian:1; // 1: big endian, 0: little endian ULONG RxThreshold:2; // Rx threshold in DW to start PCI access // 01: 8DW, 10: 4DW, 11: 32DW, default 00: 16DW ULONG TxThreshold:2; // Tx threshold in DW to start PCI access // 01: 1DW, 10: 4DW, 11: store & forward, default 00: 0DW ULONG BurstLength:2; // PCI burst length // 01: 8DW, 10: 16DW, 11:32DW, default 00: 4DW ULONG EnableClk:1; // Enable CLK_RUN, PCI clock can't going down to non-operational ULONG Rsvd:24; } field; ULONG word;} PCICSR_STRUC, *PPCICSR_STRUC;//// PWRCSR0: Power mode configuration register////// PSCSR0: Power saving delay time register 0////// PSCSR1: Power saving delay time register 1////// PSCSR2: Power saving delay time register 2////// PSCSR3: Power saving delay time register 3////// MAC_CSR17: Manual power control / status register//typedef union _MAC_CSR17_STRUC { struct { USHORT SetState:1; USHORT BbpDesireState:2; USHORT RfDesireState:2; USHORT BbpCurrState:2; USHORT RfCurrState:2; USHORT PutToSleep:1; USHORT Rsvd:6; } field; USHORT value;} MAC_CSR17_STRUC, *PMAC_CSR17_STRUC;#if 0//RT2560//// PWRCSR1: Manual power control / status register//typedef union _PWRCSR1_STRUC { struct { ULONG SetState:1; ULONG BbpDesireState:2; ULONG RfDesireState:2; ULONG BbpCurrState:2; ULONG RfCurrState:2; ULONG PutToSleep:1; ULONG Rsvd:22; } field; ULONG word;} PWRCSR1_STRUC, *PPWRCSR1_STRUC;#endif//// TIMECSR: Timer control register////// MACCSR0: MAC configuration register 0////// MACCSR1: MAC configuration register 1//typedef union _MACCSR1_STRUC { struct { ULONG KickRx:1; // Kick one-shot Rx in one-shot Rx mode ULONG OneShotRxMode:1; // Enable one-shot Rx mode for debugging ULONG BbpRxResetMode:1; // Ralink BBP RX reset mode ULONG AutoTxBbp:1; // Auto Tx logic access BBP control register ULONG AutoRxBbp:1; // Auto Rx logic access BBP control register ULONG LoopBack:2; // Loopback mode. 00: normal, 01: internal, 10: external, 11:rsvd. ULONG IntersilIF:1; // Intersil IF calibration pin ULONG Rsvd:24; } field; ULONG word;} MACCSR1_STRUC, *PMACCSR1_STRUC;//// RALINKCSR: Ralink Rx auto-reset BBCR//typedef union _RALINKCSR_STRUC { struct { ULONG ArBbpData0:8; // Auto reset BBP register 0 data ULONG ArBbpId0:7; // Auto reset BBP register 0 Id ULONG ArBbpValid0:1; // Auto reset BBP register 0 is valid ULONG ArBbpData1:8; // Auto reset BBP register 1 data ULONG ArBbpId1:7; // Auto reset BBP register 1 Id ULONG ArBbpValid1:1; // Auto reset BBP register 1 is valid } field; ULONG word;} RALINKCSR_STRUC, *PRALINKCSR_STRUC;//// BCNCSR: Beacon interval control register//typedef union _BCNCSR_STRUC { struct { ULONG Change:1; // Write one to change beacon interval ULONG DeltaTime:4; // The delta time value ULONG NumBcn:8; // Delta time value or number of beacon according to mode ULONG Mode:2; // please refer to ASIC specs. ULONG Plus:1; // plus or minus delta time value ULONG Rsvd:16; } field; ULONG word;} BCNCSR_STRUC, *PBCNCSR_STRUC;typedef union _PHY_CSR7_STRUC { struct { USHORT Data:8; // BBP data USHORT RegID:7; // BBP register ID USHORT WriteControl:1; // 1: Write, 0: Read } field; USHORT value;} PHY_CSR7_STRUC, *PPHY_CSR7_STRUC;typedef union _PHY_CSR8_STRUC { struct { USHORT Busy:1; // 1: ASIC is busy execute BBP programming. USHORT Rsvd:15; } field; USHORT value;} PHY_CSR8_STRUC, *PPHY_CSR8_STRUC;typedef union _PHY_CSR10_STRUC { struct { USHORT RFRegValue:8; // Register value (include register id) serial out to RF/IF chip. USHORT NumberOfBits:5; // Number of bits used in RFRegValue (I:20, RFMD:22) USHORT IFSelect:1; // 1: select IF to program, 0: select RF to program USHORT PLL_LD:1; // RF PLL_LD status USHORT Busy:1; // 1: ASIC is busy execute RF programming. } field; USHORT value;} PHY_CSR10_STRUC, *PPHY_CSR10_STRUC;#if 0//rt2460//// BBPCSR: BBP serial control register//typedef union _BBPCSR_STRUC { struct { ULONG Value:8; // Register value to program into BBP ULONG RegNum:7; // Selected BBP register ULONG Busy:1; // 1: ASIC is busy execute BBP programming. ULONG WriteControl:1; // 1: Write BBP, 0: Read BBP ULONG Rsvd:15; } field; ULONG word;} BBPCSR_STRUC, *PBBPCSR_STRUC;//// RFCSR: RF serial control register//typedef union _RFCSR_STRUC { struct { ULONG RFRegValue:24; // Register value (include register id) serial out to RF/IF chip. ULONG NumberOfBits:5; // Number of bits used in RFRegValue (I:20, RFMD:22) ULONG IFSelect:1; // 1: select IF to program, 0: select RF to program ULONG PLL_LD:1; // RF PLL_LD status ULONG Busy:1; // 1: ASIC is busy execute RF programming. } field; ULONG word;} RFCSR_STRUC, *PRFCSR_STRUC;#endif//// LEDCSR: LED control register//typedef union _LEDCSR_STRUC { struct { ULONG OnPeriod:8; // On period, default 70ms ULONG OffPeriod:8; // Off period, default 30ms ULONG Link:1; // 1: linkup, 0: linkoff ULONG Activity:1; // 1: active, 0: idle ULONG Rsvd:14; } field; ULONG word;} LEDCSR_STRUC, *PLEDCSR_STRUC;//// GPIOCSR: GPIO control register//typedef union _GPIOCSR_STRUC { struct { ULONG Bit0:1; ULONG Bit1:1; ULONG Bit2:1; ULONG Bit3:1; ULONG Bit4:1; ULONG Bit5:1; ULONG Bit6:1; ULONG Bit7:1; ULONG Rsvd:24; } field; ULONG word;} GPIOCSR_STRUC, *PGPIOCSR_STRUC;//// TXRX_CSR20: Tx BEACON offset time control register//typedef union _TXRX_CSR20_STRUC { struct { USHORT Offset:13; // in units of usec USHORT BeaconExpectWindow:3; // 2^CwMin } field; USHORT value;} TXRX_CSR20_STRUC, *PTXRX_CSR20_STRUC;#if 0//// BCNCSR1: Tx BEACON offset time control register//typedef union _BCNCSR1_STRUC { struct { USHORT Preload; // in units of usec USHORT Rsvd; } field; ULONG word;} BCNCSR1_STRUC, *PBCNCSR1_STRUC;#endif//// MACCSR2: TX_PE to RX_PE turn-around time control register//typedef union _MACCSR2_STRUC { struct { ULONG Delay:8; // in units of PCI clock cycle ULONG Rsvd:24; } field; ULONG word;} MACCSR2_STRUC, *PMACCSR2_STRUC;//// EEPROM antenna select format//typedef union _EEPROM_ANTENNA_STRUC { struct { USHORT NumOfAntenna:2; // Number of antenna USHORT TxDefaultAntenna:2; // default of antenna, 0: diversity, 1:antenna-A, 2:antenna-B reserved (default = 0) USHORT RxDefaultAntenna:2; // default of antenna, 0: diversity, 1:antenna-A, 2:antenna-B reserved (default = 0) USHORT LedMode:3; // 0-default mode, 1:TX/RX activity mode, 2: Single LED (didn't care about link), 3: reserved USHORT DynamicTxAgcControl:1; USHORT HardwareRadioControl:1; // 1: Hardware controlled radio enabled, Read GPIO0 required. USHORT RfType:5; // see E2PROM document } field; USHORT word;} EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;typedef union _EEPROM_NIC_CINFIG2_STRUC { struct { USHORT CardbusAcceleration:1; // !!! NOTE: 0 - enable, 1 - disable USHORT DynamicBbpTuning:1; // !!! NOTE: 0 - enable, 1 - disable USHORT CckTxPower:2; // CCK TX power compensation USHORT Rsv:12; // must be 0 } field; USHORT word;} EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;typedef union _EEPROM_TX_PWR_STRUC { struct { UCHAR Byte0; // Low Byte UCHAR Byte1; // High Byte } field; USHORT word;} EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;#endif // __RT2570_H__⌨️ 快捷键说明
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