integrator.h

s2410测试程序,源码,用来深入了解三星2410芯片

#define PCI_IO_ADR1             PCI_IO_ADR0 + PCI_IO_SIZE
#define PCI_IO_SIZE1            PCI_IO_SIZE
#define PCI_INT_LVL1            INT_LVL_PCI_1
#define PCI_INT_VEC1            INT_VEC_PCI_1

#define PCI_MEM_ADR2            PCI_MEM_ADR1 + PCI_MEM_SIZE
#define PCI_IO_ADR2             PCI_IO_ADR1 + PCI_IO_SIZE
#define PCI_IO_SIZE2            PCI_IO_SIZE
#define PCI_INT_LVL2            INT_LVL_PCI_2
#define PCI_INT_VEC2            INT_VEC_PCI_2


/* PCI memory base address register configuration mode */

#define FORCE		0x00	/* overwrite membase address register */
#define AUTO		0x01	/* read membase address register */

/*
 * Need to use automatic configuration mode using the resource assigning in
 * pciAssignResources().
 */

#define PCI_REG_MOD	AUTO	/* define the register configuration mode */

#define TYPE_ALLOC	1000

/*
 * Definitions for Ethernet driver buffer use.
 *
 * The buffers to be shared across the PCI bus in must not have addresses
 * in low memory which refer to header card SSRAM (which is not
 * reachable from the PCI bus). We can do several things:
 *
 * 1. Simply allow the driver to use use cacheDmaMalloc() without
 * checking the addresses returned. Because of where the heap usually
 * is, cacheDmaMalloc() in default kernels will generally return
 * addresses which are "low-aliases" for SDRAM and not header card SSRAM.
 * To use this option, do not define INTEGRATOR_ENET_FIXED_BUF_ADRS and do
 * not define the parameter INTEGRATOR_ENET_CHECK_BUFFERS. Header cards for
 * later CPUs may have more local SSRAM, so this may become more of a problem
 * with those later cards.
 *
 * 2. Use cacheDmaMalloc() in the BSP initialisation code, but check that the
 * memory returned is not, in fact, SSRAM, but is actually SDRAM. To use this
 * option define the parameter INTEGRATOR_ENET_CHECK_BUFFERS. A disadvantage
 * of this is that the BSP then needs knowledge of the relationship between
 * buffer space required and the numbers of transmit and receive buffers to be
 * allocated, which would normally be kept within the driver. This is the
 * option configured by default.
 *
 * 3. Define the buffer address to be a specific address, which is
 * accessible from the PCI bus.
 * (a) One possibility is the unaliased SDRAM at its real (high) address.
 * To use this option, define INTEGRATOR_ENET_FIXED_BUF_ADRS and define
 * INTEGRATOR_XXX_BUF_ADRS to be INTEGRATOR_SDRAM_ALIAS_BASE.
 * All of the SDRAM is mapped at the high address, but the size of the
 * part that is not aliased down to low memory, will be the size of the
 * header card SSRAM. On 720T, there is 256 Kbytes and on 920T, we have 1
 * megabyte.
 * (b) Another possibility is the motherboard SSRAM, though early
 * motherboards have a fault that prevents this SSRAM from being accessed
 * from PCI unless the FPGAs on the board have been upgraded. To use this
 * option, define INTEGRATOR_ENET_FIXED_BUF_ADRS and define
 * INTEGRATOR_ENET_XXX_BUF_ADRS to be INTEGRATOR_MBRD_SSRAM_ALIAS_BASE
 * (+ offset if required).
 *
 * In the FEI driver, we use ((nCFDs + 5*nRFDs) * 1544) + 4 bytes.
 * On 720T, this is more than the size of the unaliased SDRAM (256 kbytes),
 * so if we use that area, we need to adjust the number of CFDs and
 * RFDs downwards slightly.
 *
 * Note that all of the fixed address options listed above will suffer a
 * performance penalty over using low-aliased-SDRAM.
 *
 * 4. Reserve an area of SDRAM (at the low alias, but above the end of
 * header card SSRAM) to use for the buffer memory.
 *
 * The drivers will check that the amount of memory given is sufficient
 * for the numbers of CFDs and RFDs and will fail to load if there is a
 * mismatch.
 *
 * Obviously, if only one of the FEI and DEC drivers is being used, then buffer
 * space need only be allocated for the one being used.
 */

#undef  INTEGRATOR_ENET_FIXED_BUF_ADRS	/* do not use fixed address bufs */
#define INTEGRATOR_ENET_CHECK_BUFFERS	/* check cacheDmaMalloc() addresses */


#ifdef  INTEGRATOR_ENET_FIXED_BUF_ADRS

/*
 * Provide definitions for the buffer address for the three possible PCI cards.
 * The SDRAM alias address should be available on all boards.
 */

#define INTEGRATOR_ENET_PRIMARY_BUF_ADRS INTEGRATOR_SDRAM_ALIAS_BASE

/* next two areas require a later board, or the FPGAs to have been upgraded */

#define INTEGRATOR_ENET_SECONDARY_BUF_ADRS INTEGRATOR_MBRD_SSRAM_BASE
#define INTEGRATOR_ENET_TERTIARY_BUF_ADRS (INTEGRATOR_MBRD_SSRAM_BASE + 0x40000)
#endif /* INTEGRATOR_ENET_FIXED_BUF_ADRS */


#define INTEGRATOR_DEC_BUF_SIZE	0x30000

/*
 * Assuming we are on a 720T, and three drivers are being started, the
 * smallest slot is 256 kbytes, so reduce memory usage to fit into 256 Kbyte
 * slot. This can be overridden, if we know differently.
 */

#if defined (INTEGRATOR_ENET_FIXED_BUF_ADRS)
#define INTEGRATOR_FEI_BUF_SIZE	0x40000
#define INTEGRATOR_FEI_NUM_CFDS	28
#define INTEGRATOR_FEI_NUM_RFDS	28
#else
#define INTEGRATOR_FEI_BUF_SIZE	0x49000
#define INTEGRATOR_FEI_NUM_CFDS	32
#define INTEGRATOR_FEI_NUM_RFDS	32
#endif


/*
 * Max number of END devices we support - we currently set to three for
 * three PCI slots.
 */

#define INTEGRATOR_MAX_END_DEVS 3

/*
 * Max number of VGA devices we support - we currently set to three for
 * three PCI slots.
 */

#define INTEGRATOR_MAX_VGA_DEVS 3


/* Definitions for LED controller and sysLedsReadWrite */

#define LED_BASE        0x1A000000
#define LED_ALPHA 	(LED_BASE + 0x00)
#define LED_LIGHTS	(LED_BASE + 0x04)
#define LED_SWITCHES	(LED_BASE + 0x08)

#define LED_STATUS	0x01

#define LED_0		0x01
#define LED_1		0x02
#define LED_2		0x04
#define LED_4		0x08

#define LED_LEDS_MASK	0x0F


#define ARM966_I_SRAM_ENABLE    (1<<12)
#define ARM966_WBUFF_ENABLE     (1<<3)
#define ARM966_D_SRAM_ENABLE    (1<<2)

#ifdef __cplusplus
}
#endif


#ifdef __cplusplus
extern "C" {
#endif

#define TARGET_INTEGRATOR

/* Flash definitions */

#define FLASH_BASE		0x00000000	/* Base address of Flash part */
#define FLASH_BLOCK_NUM		128		/* 128 kB block used as NVRAM */
#define FLASH_ADRS				(FLASH_BASE + (FLASH_BLOCK_NUM * 0x20000))
#define INTEGRATOR_FLASH_SIZE 	0x01000000 	/* Total Flash available. */
#define FLASH_WIDTH		4	  	/* Two 16-bit wide parts */
#define FLASH_CHIP_WIDTH        2
#define FLASH_WIDTH_SPECIAL_2			/* see flash28.h */
#define SYS_FLASH_WRITE				/* use enable/disable routines*/

/*
 * It is not necessary to define SYS_FLASH_TYPE as FLASH_28F320 as
 * auto-identification correctly identifies the Flash part.
 */



#define S3C2410_INT_NUM_LEVELS	32	/* Lizm, FIXED */


/* Interrupt levels */

#define INT_LVL_SOFT		0	/* soft interrupt */
#define INT_LVL_UART_0  	1	/* UART 0 */
#define INT_LVL_UART_1		2	/* UART 1 */
#define INT_LVL_KEYBOARD	3	/* keyboard interrupt */
#define INT_LVL_MOUSE		4	/* mouse interrupt */
#define INT_LVL_TIMER_0		5	/* timer 0 */
#define INT_LVL_TIMER_1		6	/* timer 1 */
#define INT_LVL_TIMER_2		7	/* timer 2 */
#define INT_LVL_RTC		8	/* real-time clock */
#define INT_LVL_EXP0		9	/* logic module 0 */
#define INT_LVL_EXP1		10	/* logic module 1 */
#define INT_LVL_EXP2		11	/* logic module 2 */
#define INT_LVL_EXP3		12	/* logic module 3 */
#define INT_LVL_PCI_0		13	/* PCI int A */
#define INT_LVL_PCI_1		14	/* PCI int B */
#define INT_LVL_PCI_2		15	/* PCI int C */
#define INT_LVL_PCI_3		16	/* PCI int D */
#define INT_LVL_PCIBRIDGE	17	/* V3 PCI bridge interrupt */
#define INT_LVL_DEG		18	/* CompactPCI aux (DEG#) */
#define INT_LVL_ENUM		19	/* CompactPCI aux (ENUM#) */
#define INT_LVL_PCILB		20	/* PCI local bus fault */
#define INT_LVL_APC		21	/* AutoPC external int */

/* Interrupr Level FIXED, Lizm */
#undef  INT_LVL_UART_0
#undef  INT_LVL_UART_1
#undef  INT_LVL_UART_2
#undef  INT_LVL_TIMER_0	
#undef  INT_LVL_TIMER_1	
#undef  INT_LVL_TIMER_2	
#undef  INT_LVL_TIMER_3	
#undef  INT_LVL_TIMER_4	
#undef  INT_LVL_RTC
#undef  INT_LVL_TICK	
#undef  INT_LVL_WDT	

#define INT_LVL_TICK		8	
#define INT_LVL_WDT		9
#define INT_LVL_TIMER_0		10	/* timer 0 */
#define INT_LVL_TIMER_1		11	/* timer 1 */
#define INT_LVL_TIMER_2		12	/* timer 2 */
#define INT_LVL_TIMER_3		13	/* timer 3 */
#define INT_LVL_TIMER_4		14	/* timer 4 */
#define INT_LVL_UART_2		15	/* UART 2 */
#define INT_LVL_UART_1		23	/* UART 1 */
#define INT_LVL_UART_0  	28	/* UART 0 */
#define INT_LVL_RTC		30	/* real-time clock */

/* interrupt vectors */

#define INT_VEC_SOFT		IVEC_TO_INUM(INT_LVL_SOFT)
#define INT_VEC_UART_0		IVEC_TO_INUM(INT_LVL_UART_0)
#define INT_VEC_UART_1		IVEC_TO_INUM(INT_LVL_UART_1)
#define INT_VEC_KEYBOARD	IVEC_TO_INUM(INT_LVL_KEYBOARD)
#define INT_VEC_MOUSE		IVEC_TO_INUM(INT_LVL_MOUSE)
#define INT_VEC_TIMER_0		IVEC_TO_INUM(INT_LVL_TIMER_0)
#define INT_VEC_TIMER_1		IVEC_TO_INUM(INT_LVL_TIMER_1)
#define INT_VEC_TIMER_2		IVEC_TO_INUM(INT_LVL_TIMER_2)
#define INT_VEC_RTC	        IVEC_TO_INUM(INT_LVL_RTC)
#define INT_VEC_EXP0		IVEC_TO_INUM(INT_LVL_EXP0)
#define INT_VEC_EXP1		IVEC_TO_INUM(INT_LVL_EXP1)
#define INT_VEC_EXP2		IVEC_TO_INUM(INT_LVL_EXP2)
#define INT_VEC_EXP3		IVEC_TO_INUM(INT_LVL_EXP3)
#define INT_VEC_PCI_0		IVEC_TO_INUM(INT_LVL_PCI_0)
#define INT_VEC_PCI_1		IVEC_TO_INUM(INT_LVL_PCI_1)
#define INT_VEC_PCI_2		IVEC_TO_INUM(INT_LVL_PCI_2)
#define INT_VEC_PCI_3		IVEC_TO_INUM(INT_LVL_PCI_3)
#define INT_VEC_PCIBRIDGE	IVEC_TO_INUM(INT_LVL_PCIBRIDGE)
#define INT_VEC_DEG		IVEC_TO_INUM(INT_LVL_DEG)
#define INT_VEC_ENUM		IVEC_TO_INUM(INT_LVL_ENUM)
#define INT_VEC_PCILB		IVEC_TO_INUM(INT_LVL_PCILB)
#define INT_VEC_APC		IVEC_TO_INUM(INT_LVL_APC)

/* Interrupr vectors FIXED, Lizm */
#undef  INT_VEC_UART_0
#undef  INT_VEC_UART_1
#undef  INT_VEC_UART_2
#undef  INT_VEC_TIMER_0	
#undef  INT_VEC_TIMER_1	
#undef  INT_VEC_TIMER_2	
#undef  INT_VEC_TIMER_3	
#undef  INT_VEC_TIMER_4	
#undef  INT_VEC_RTC
#undef  INT_VEC_TICK	
#undef  INT_VEC_WDT	
            
#define INT_VEC_TICK		IVEC_TO_INUM(INT_LVL_TICK	)
#define INT_VEC_WDT		IVEC_TO_INUM(INT_LVL_WDT	)
#define INT_VEC_TIMER_0		IVEC_TO_INUM(INT_LVL_TIMER_0	)
#define INT_VEC_TIMER_1		IVEC_TO_INUM(INT_LVL_TIMER_1	)
#define INT_VEC_TIMER_2		IVEC_TO_INUM(INT_LVL_TIMER_2	)
#define INT_VEC_TIMER_3		IVEC_TO_INUM(INT_LVL_TIMER_3	)
#define INT_VEC_TIMER_4		IVEC_TO_INUM(INT_LVL_TIMER_4	)
#define INT_VEC_UART_2		IVEC_TO_INUM(INT_LVL_UART_2	)
#define INT_VEC_UART_1		IVEC_TO_INUM(INT_LVL_UART_1	)
#define INT_VEC_UART_0  	IVEC_TO_INUM(INT_LVL_UART_0  	)
#define INT_VEC_RTC		IVEC_TO_INUM(INT_LVL_RTC	)

/* definitions for the AMBA UART */


#define UART_XTAL_FREQ		S3C2410_UARTCLK /* UART baud rate clk freq */
#define N_SIO_CHANNELS		N_AMBA_UART_CHANNELS
#define N_UART_CHANNELS		N_AMBA_UART_CHANNELS
#define N_AMBA_UART_CHANNELS	2		/* number of AMBA UART chans */

#define UART_0_BASE_ADR		0x50000000	/* UART 0 base address, Lizm Fixed */
#define UART_1_BASE_ADR		0x50004000	/* UART 1 base address, Lizm Fixed */



#define SYS_TIMER_INT_LVL (INT_LVL_TIMER_0)
#define AUX_TIMER_INT_LVL (INT_LVL_TIMER_1)

/* Add corresponding INT_VEC definitions for intConnect calls. */

#define SYS_TIMER_INT_VEC (INT_VEC_TIMER_0)
#define AUX_TIMER_INT_VEC (INT_VEC_TIMER_1)

/* Frequency of counter/timers */

#define S3C2410_SYSCLK   200800000			/* System clock */
#define S3C2410_P_CLK    (S3C2410_SYSCLK/4)
#define S3C2410_UARTCLK  (S3C2410_P_CLK/16)		/* UART clock */

#define SYS_TIMER_CLK	(S3C2410_P_CLK)
#define AUX_TIMER_CLK	(S3C2410_P_CLK)

/* Bit field definitions */

#define BIT0                            0x00000001
#define BIT1                            0x00000002
#define BIT2                            0x00000004
#define BIT3                            0x00000008
#define BIT4                            0x00000010
#define BIT5                            0x00000020
#define BIT6                            0x00000040
#define BIT7                            0x00000080
#define BIT8                            0x00000100
#define BIT9                            0x00000200
#define BIT10                           0x00000400
#define BIT11                           0x00000800
#define BIT12                           0x00001000
#define BIT13                           0x00002000
#define BIT14                           0x00004000
#define BIT15                           0x00008000
#define BIT16                           0x00010000
#define BIT17                           0x00020000
#define BIT18                           0x00040000
#define BIT19                           0x00080000
#define BIT20                           0x00100000

/* Handy sizes */

#define SZ_1K                           0x00000400
#define SZ_4K                           0x00001000
#define SZ_8K                           0x00002000
#define SZ_16K                          0x00004000
#define SZ_64K                          0x00010000
#define SZ_128K                         0x00020000
#define SZ_256K                         0x00040000
#define SZ_512K                         0x00080000

#define SZ_1M                           0x00100000
#define SZ_2M                           0x00200000
#define SZ_4M                           0x00400000
#define SZ_8M                           0x00800000
#define SZ_16M                          0x01000000
#define SZ_32M                          0x02000000
#define SZ_64M                          0x04000000
#define SZ_128M                         0x08000000
#define SZ_256M                         0x10000000
#define SZ_512M                         0x20000000

#define SZ_1G                           0x40000000
#define SZ_2G                           0x80000000


#ifdef __cplusplus
}
#endif

#endif	/* INCintegratorh */