integrator.h

s2410测试程序,源码,用来深入了解三星2410芯片

#define INT_LVL_PCI_0		13	/* PCI int A */
#define INT_LVL_PCI_1		14	/* PCI int B */
#define INT_LVL_PCI_2		15	/* PCI int C */
#define INT_LVL_PCI_3		16	/* PCI int D */
#define INT_LVL_PCIBRIDGE	17	/* V3 PCI bridge interrupt */
#define INT_LVL_DEG		18	/* CompactPCI aux (DEG#) */
#define INT_LVL_ENUM		19	/* CompactPCI aux (ENUM#) */
#define INT_LVL_PCILB		20	/* PCI local bus fault */
#define INT_LVL_APC		21	/* AutoPC external int */


/* interrupt vectors */

#define INT_VEC_SOFT		IVEC_TO_INUM(INT_LVL_SOFT)
#define INT_VEC_UART_0		IVEC_TO_INUM(INT_LVL_UART_0)
#define INT_VEC_UART_1		IVEC_TO_INUM(INT_LVL_UART_1)
#define INT_VEC_KEYBOARD	IVEC_TO_INUM(INT_LVL_KEYBOARD)
#define INT_VEC_MOUSE		IVEC_TO_INUM(INT_LVL_MOUSE)
#define INT_VEC_TIMER_0		IVEC_TO_INUM(INT_LVL_TIMER_0)
#define INT_VEC_TIMER_1		IVEC_TO_INUM(INT_LVL_TIMER_1)
#define INT_VEC_TIMER_2		IVEC_TO_INUM(INT_LVL_TIMER_2)
#define INT_VEC_RTC		IVEC_TO_INUM(INT_LVL_RTC)
#define INT_VEC_EXP0		IVEC_TO_INUM(INT_LVL_EXP0)
#define INT_VEC_EXP1		IVEC_TO_INUM(INT_LVL_EXP1)
#define INT_VEC_EXP2		IVEC_TO_INUM(INT_LVL_EXP2)
#define INT_VEC_EXP3		IVEC_TO_INUM(INT_LVL_EXP3)
#define INT_VEC_PCI_0		IVEC_TO_INUM(INT_LVL_PCI_0)
#define INT_VEC_PCI_1		IVEC_TO_INUM(INT_LVL_PCI_1)
#define INT_VEC_PCI_2		IVEC_TO_INUM(INT_LVL_PCI_2)
#define INT_VEC_PCI_3		IVEC_TO_INUM(INT_LVL_PCI_3)
#define INT_VEC_PCIBRIDGE	IVEC_TO_INUM(INT_LVL_PCIBRIDGE)
#define INT_VEC_DEG		IVEC_TO_INUM(INT_LVL_DEG)
#define INT_VEC_ENUM		IVEC_TO_INUM(INT_LVL_ENUM)
#define INT_VEC_PCILB		IVEC_TO_INUM(INT_LVL_PCILB)
#define INT_VEC_APC		IVEC_TO_INUM(INT_LVL_APC)


/* definitions for the AMBA UART */

#define UART_XTAL_FREQ		INTEGRATOR_UARTCLK /* UART baud rate clk freq */
#define N_SIO_CHANNELS		N_AMBA_UART_CHANNELS
#define N_UART_CHANNELS		N_AMBA_UART_CHANNELS
#define N_AMBA_UART_CHANNELS	2		/* number of AMBA UART chans */

#define UART_0_BASE_ADR		0x16000000	/* UART 0 base address */
#define UART_1_BASE_ADR		0x17000000	/* UART 1 base address */

/* definitions for the keyboard */
#define KBD_BASE_ADR		0x18000000	/* Keyboard 0 base address */
#define MOUSE_BASE_ADR		0x19000000	/* Mouse 1 base address */

#define KBD_REGS_SIZE           0x14
#define MOUSE_REGS_SIZE         0x14

/* definitions for the AMBA Timer */

#define AMBA_TIMER_BASE		0x13000000	/* Address of base of timer */
#define AMBA_BASE_OFFSET        0X100


#define AMBA_TIMER0_BASE ((AMBA_TIMER_BASE))
#define AMBA_TIMER1_BASE ((AMBA_TIMER_BASE) + AMBA_BASE_OFFSET)
#define AMBA_TIMER2_BASE ((AMBA_TIMER_BASE) + 2 * AMBA_BASE_OFFSET)

#define SYS_TIMER_BASE AMBA_TIMER0_BASE
#define AUX_TIMER_BASE AMBA_TIMER1_BASE

#define SYS_TIMER_INT_LVL (INT_LVL_TIMER_0)
#define AUX_TIMER_INT_LVL (INT_LVL_TIMER_1)

/* Add corresponding INT_VEC definitions for intConnect calls. */

#define SYS_TIMER_INT_VEC (INT_VEC_TIMER_0)
#define AUX_TIMER_INT_VEC (INT_VEC_TIMER_1)

#define AMBA_TIMER_SYS_TC_DISABLE	(TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define AMBA_TIMER_SYS_TC_ENABLE	(TC_ENABLE  | TC_PERIODIC | TC_DIV16)
#define AMBA_TIMER_AUX_TC_DISABLE	(TC_DISABLE | TC_PERIODIC | TC_DIV16)
#define AMBA_TIMER_AUX_TC_ENABLE	(TC_ENABLE  | TC_PERIODIC | TC_DIV16)

/* Frequency of counter/timers */

#define SYS_TIMER_CLK	(INTEGRATOR_SYSCLK/16)
#define AUX_TIMER_CLK	(INTEGRATOR_CLK24MHZ/16)

#define AMBA_RELOAD_TICKS	0	/* No overhead */

/* Mask out unused bits from timer register. */

#define AMBA_TIMER_VALUE_MASK	0xFFFF

/* Sys Clk is timer 1 */

#define SYS_TIMER_CLEAR AMBA_TIMER_T1CLEAR
#define SYS_TIMER_CTRL  AMBA_TIMER_T1CTRL
#define SYS_TIMER_LOAD  AMBA_TIMER_T1LOAD
#define SYS_TIMER_VALUE AMBA_TIMER_T1VALUE

/* Aux Clk is timer 2 */

#define AUX_TIMER_CLEAR AMBA_TIMER_T2CLEAR
#define AUX_TIMER_CTRL  AMBA_TIMER_T2CTRL
#define AUX_TIMER_LOAD  AMBA_TIMER_T2LOAD
#define AUX_TIMER_VALUE AMBA_TIMER_T2VALUE


/*
 * Clock rates depend upon CPU power and work load of application.
 * The values below are minimum and maximum allowed by the hardware.
 * So:
 * min frequency = roundup(clock_rate/(max_counter_value))
 * max frequency = rounddown(clock_rate/(min_counter_value))
 * i.e. SYS_CLK_RATE_MAX = SYS_TIMER_CLK
 *      AUX_CLK_RATE_MAX = AUX_TIMER_CLK
 *
 * However, we must set maxima that are sustainable on a running
 * system determined by experimentation.
 *
 * The 720T values have been determined by experimentation, the others
 * need to be checked.
 */

#define SYS_CLK_RATE_MIN ((SYS_TIMER_CLK+0xFFFF)/0x10000)
#if defined(CPU_720T) || defined(CPU_720T_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_740T) || defined(CPU_740T_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_920T) || defined(CPU_920T_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_940T) || defined(CPU_940T_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_946ES) || defined(CPU_946ES_T)
#define SYS_CLK_RATE_MAX 25000
#elif defined(CPU_966ES) || defined(CPU_966ES_T)
#define SYS_CLK_RATE_MAX 6000
#else
#define SYS_CLK_RATE_MAX 9000
#endif

#define AUX_CLK_RATE_MIN ((AUX_TIMER_CLK+0xFFFF)/0x10000)
#if defined(CPU_720T) || defined(CPU_720T_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_740T) || defined(CPU_740T_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_920T) || defined(CPU_920T_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_940T) || defined(CPU_940T_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_946ES) || defined(CPU_946ES_T)
#define AUX_CLK_RATE_MAX 25000
#elif defined(CPU_966ES) || defined(CPU_966ES_T)
#define AUX_CLK_RATE_MAX 6000
#else
#define AUX_CLK_RATE_MAX 9000
#endif


/* PCI definitions */

/* Interrupt number for PCI */

#define INT_NUM_IRQ0	INT_LVL_PCI_0

/* V3 PCI bridge controller */

#define V3_BASE		0x62000000    /* V360EPC registers */

/* Bit field definitions */

#define BIT0                            0x00000001
#define BIT1                            0x00000002
#define BIT2                            0x00000004
#define BIT3                            0x00000008
#define BIT4                            0x00000010
#define BIT5                            0x00000020
#define BIT6                            0x00000040
#define BIT7                            0x00000080
#define BIT8                            0x00000100
#define BIT9                            0x00000200
#define BIT10                           0x00000400
#define BIT11                           0x00000800
#define BIT12                           0x00001000
#define BIT13                           0x00002000
#define BIT14                           0x00004000
#define BIT15                           0x00008000
#define BIT16                           0x00010000
#define BIT17                           0x00020000
#define BIT18                           0x00040000
#define BIT19                           0x00080000
#define BIT20                           0x00100000

/* Handy sizes */

#define SZ_1K                           0x00000400
#define SZ_4K                           0x00001000
#define SZ_8K                           0x00002000
#define SZ_16K                          0x00004000
#define SZ_64K                          0x00010000
#define SZ_128K                         0x00020000
#define SZ_256K                         0x00040000
#define SZ_512K                         0x00080000

#define SZ_1M                           0x00100000
#define SZ_2M                           0x00200000
#define SZ_4M                           0x00400000
#define SZ_8M                           0x00800000
#define SZ_16M                          0x01000000
#define SZ_32M                          0x02000000
#define SZ_64M                          0x04000000
#define SZ_128M                         0x08000000
#define SZ_256M                         0x10000000
#define SZ_512M                         0x20000000

#define SZ_1G                           0x40000000
#define SZ_2G                           0x80000000


/* V3 Local Bus to PCI Bridge definitions */

#define V3_PCI_VENDOR                   0x00000000
#define V3_PCI_DEVICE                   0x00000002
#define V3_PCI_CMD                      0x00000004
#define V3_PCI_STAT                     0x00000006
#define V3_PCI_CC_REV                   0x00000008
#define V3_PCI_HDR_CFG                  0x0000000C
#define V3_PCI_IO_BASE                  0x00000010
#define V3_PCI_BASE0                    0x00000014
#define V3_PCI_BASE1                    0x00000018
#define V3_PCI_SUB_VENDOR               0x0000002C
#define V3_PCI_SUB_ID                   0x0000002E
#define V3_PCI_ROM                      0x00000030
#define V3_PCI_BPARAM                   0x0000003C
#define V3_PCI_MAP0                     0x00000040
#define V3_PCI_MAP1                     0x00000044
#define V3_PCI_INT_STAT                 0x00000048
#define V3_PCI_INT_CFG                  0x0000004C
#define V3_LB_BASE0                     0x00000054
#define V3_LB_BASE1                     0x00000058
#define V3_LB_MAP0                      0x0000005E
#define V3_LB_MAP1                      0x00000062
#define V3_LB_BASE2                     0x00000064
#define V3_LB_MAP2                      0x00000066
#define V3_LB_SIZE                      0x00000068
#define V3_LB_IO_BASE                   0x0000006E
#define V3_FIFO_CFG                     0x00000070
#define V3_FIFO_PRIORITY                0x00000072
#define V3_FIFO_STAT                    0x00000074
#define V3_LB_ISTAT                     0x00000076
#define V3_LB_IMASK                     0x00000077
#define V3_SYSTEM                       0x00000078
#define V3_LB_CFG                       0x0000007A
#define V3_PCI_CFG                      0x0000007C
#define V3_DMA_PCI_ADR0                 0x00000080
#define V3_DMA_PCI_ADR1                 0x00000090
#define V3_DMA_LOCAL_ADR0               0x00000084
#define V3_DMA_LOCAL_ADR1               0x00000094
#define V3_DMA_LENGTH0                  0x00000088
#define V3_DMA_LENGTH1                  0x00000098
#define V3_DMA_CSR0                     0x0000008B
#define V3_DMA_CSR1                     0x0000009B
#define V3_DMA_CTLB_ADR0                0x0000008C
#define V3_DMA_CTLB_ADR1                0x0000009C
#define V3_DMA_DELAY                    0x000000E0
#define V3_MAIL_DATA                    0x000000C0
#define V3_PCI_MAIL_IEWR                0x000000D0
#define V3_PCI_MAIL_IERD                0x000000D2
#define V3_LB_MAIL_IEWR                 0x000000D4
#define V3_LB_MAIL_IERD                 0x000000D6
#define V3_MAIL_WR_STAT                 0x000000D8
#define V3_MAIL_RD_STAT                 0x000000DA
#define V3_QBA_MAP                      0x000000DC

/* SYSTEM register bits */

#define V3_SYSTEM_M_RST_OUT             BIT15
#define V3_SYSTEM_M_LOCK                BIT14

/*  PCI_CFG bits */

#define V3_PCI_CFG_M_RETRY_EN           BIT10
#define V3_PCI_CFG_M_AD_LOW1            BIT9
#define V3_PCI_CFG_M_AD_LOW0            BIT8

/* PCI MAP register bits (PCI -> Local bus) */

#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
#define V3_PCI_MAP_M_RD_POST_INH        BIT15
#define V3_PCI_MAP_M_ROM_SIZE           BIT11+BIT10
#define V3_PCI_MAP_M_SWAP               BIT9+BIT8
#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
#define V3_PCI_MAP_M_REG_EN             BIT1
#define V3_PCI_MAP_M_ENABLE             BIT0

/* 9 => 512M window size */

#define V3_PCI_MAP_M_ADR_SIZE_512M      0x00000090

/* A => 1024M window size */

#define V3_PCI_MAP_M_ADR_SIZE_1024M     0x000000A0

/* LB_BASE register bits (Local bus -> PCI) */

#define V3_LB_BASE_M_MAP_ADR            0xFFF00000
#define V3_LB_BASE_M_SWAP               BIT9+BIT8
#define V3_LB_BASE_M_ADR_SIZE           0x000000F0
#define V3_LB_BASE_M_PREFETCH           BIT3
#define V3_LB_BASE_M_ENABLE             BIT0

/* LB_MAP register bits (Local bus -> PCI) */

#define V3_LB_MAP_M_MAP_ADR             0xFFF0
#define V3_LB_MAP_M_TYPE                0x000E
#define V3_LB_MAP_M_AD_LOW_EN           BIT0

/* PCI COMMAND REGISTER bits */

#define V3_COMMAND_M_FBB_EN             BIT9
#define V3_COMMAND_M_SERR_EN            BIT8
#define V3_COMMAND_M_PAR_EN             BIT6
#define V3_COMMAND_M_MASTER_EN          BIT2
#define V3_COMMAND_M_MEM_EN             BIT1
#define V3_COMMAND_M_IO_EN              BIT0

/* size of area defined in memory map for V3 registers */

#define V3_REGS_SIZE			0x10000


/* defines for generic pciIoMapLib.c code */

#define PCI_IN_BYTE(x)		*(volatile UINT8 *) (x)
#define PCI_OUT_BYTE(x,y)	*(volatile UINT8 *) (x) = (UINT8)  y
#define PCI_IN_WORD(x)		*(volatile UINT16 *)(x)
#define PCI_OUT_WORD(x,y)	*(volatile UINT16 *)(x) = (UINT16) y
#define PCI_IN_LONG(x)		*(volatile UINT32 *)(x)
#define PCI_OUT_LONG(x,y)	*(volatile UINT32 *)(x) = (UINT32) y

/* restrict use to the first bus, by default */

#define PCI_MAX_BUS 1

/* memory map as seen by the CPU on the local bus */

#define CPU_PCI_IO_ADRS		0x60000000 	/* PCI I/O space base */
#define CPU_PCI_IO_SIZE		0x10000

#define CPU_PCI_CNFG_ADRS	0x61000000	/* PCI config space */
#define CPU_PCI_CNFG_SIZE	0x1000000

#define CPU_PCI_MEM_ADRS	0x40000000
#define CPU_PCI_MEM_SIZE	0x10000000

/* PCI view of PCI space for PCI devices */

#define PCI_IO_ADRS             0x00000000      /* base of PCI I/O address */
#define PCI2DRAM_BASE_ADRS      0x80000000      /* memory seen from PCI bus */

/* PCI view of PCI memory space for PCI memory devices */

#define PCI_MEM_ADRS		0x40000000	/* base of PCI memory space */

/* PCI address to CPU address offset */

#define PCI2CPU_IO_OFFSET	(CPU_PCI_IO_ADRS - PCI_IO_ADRS)
#define PCI2CPU_MEM_OFFSET	(CPU_PCI_MEM_ADRS - PCI_MEM_ADRS)

/* PCI bus resources */

#define PCI_IO_SIZE		0x00004000	/* PCI I/O slot size */
#define PCI_MEM_SIZE		0x00004000	/* PCI memory slot size */

#define PCI_MEM_ADR0            PCI_MEM_ADRS
#define PCI_IO_ADR0             PCI_IO_ADRS     /* I/O base for CSR 32Bytes */
#define PCI_IO_SIZE0            PCI_IO_SIZE     /* I/O size for CSR */
#define PCI_INT_LVL0            INT_LVL_PCI_0	/* Interrupt level */
#define PCI_INT_VEC0            INT_VEC_PCI_0	/* Interrupt vector */

#define PCI_MEM_ADR1            PCI_MEM_ADR0 + PCI_MEM_SIZE