📄 integrator.h
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/* integrator.h - ARM Integrator header file *//* Copyright 1999-2002 Wind River Systems, Inc. *//* Copyright 1999-2000 ARM Limited *//*modification history--------------------01q,16jul02,m_h C++ protection01p,24apr02,to fixed PCI_MEM_ADRS. defined macros for PCI to CPU offset.01o,10jan02,m_h fix NVRAM01n,31oct01,rec use generic driver for amba timer01m,09oct01,jpd added 946ES speed definitions.01l,09oct01,m_h PCI requires larger memory size for windML01k,22jun01,m_h WindML support01j,04jun01,rec memory clock rate changes for 740t01i,21feb01,h_k added support for ARM966ES and ARM966ES_T.01h,24nov00,jpd added header card SSRAM size and Ethernet definitions; added header card speed definitions; moved NVRAM Flash for more ROMmed code space; reworked PCI memory and I/O space allocations;01g,15sep00,rec add definition for INTEGRATOR_MAX_END_DEVS01f,14jun00,pr added EBI_LOCK definitions.01e,18feb00,jpd moved FOOTER to config.h.01d,07feb00,jpd added Flash definitions.01c,13jan00,pr added support for Integrator 740T.01b,07dec99,pr add support for PCI.01a,08nov99,ajb modified from pid7t template.*//*This file contains I/O address and related constants for the ARMIntegrator board.*/#ifndef INCintegratorh#define INCintegratorh#ifdef __cplusplusextern "C" {#endif#define TARGET_INTEGRATOR/* Flash definitions */#define FLASH_BASE 0x24000000 /* Base address of Flash part */#define FLASH_BLOCK_NUM 254 /* 128 kB block used as NVRAM */#define FLASH_ADRS (FLASH_BASE + (FLASH_BLOCK_NUM * 0x20000))#define INTEGRATOR_FLASH_SIZE 0x02000000 /* Total Flash available. */#define FLASH_WIDTH 4 /* Two 16-bit wide parts */#define FLASH_CHIP_WIDTH 2#define FLASH_WIDTH_SPECIAL_2 /* see flash28.h */#define SYS_FLASH_WRITE /* use enable/disable routines*//* * It is not necessary to define SYS_FLASH_TYPE as FLASH_28F320 as * auto-identification correctly identifies the Flash part. *//* Integrator memory map */#define INTEGRATOR_PERIPHERAL_BASE 0x10000000#define INTEGRATOR_PERIPHERAL_SIZE 0x10000000#define INTEGRATOR_BOOT_ROM_LO 0x00000000#define INTEGRATOR_BOOT_ROM_HI 0x20000000#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI#define INTEGRATOR_BOOT_ROM_SIZE 0x00080000/* * New Core Modules have different amounts of SSRAM, * the amount of SSRAM fitted can be found in HDR_STAT. * * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this * now refers to the minimum amount of SSRAM fitted on any * core module. * * New Core Modules also alias the SSRAM. */#define INTEGRATOR_SSRAM_BASE 0x00000000#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000#define INTEGRATOR_SSRAM_SIZE SZ_256K#if defined(CPU_920T) || defined(CPU_920T_T) || \ defined(CPU_946ES) || defined(CPU_946ES_T) || \ defined(CPU_966ES) || defined(CPU_966ES_T)#define INTEGRATOR_HDR_SSRAM_SIZE SZ_1M#else#define INTEGRATOR_HDR_SSRAM_SIZE SZ_256K#endif#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K/* SDRAM is a DIMM therefore the size is not known. */#define INTEGRATOR_SDRAM_BASE 0x00040000#define INTEGRATOR_SDRAM_ALIAS_BASE 0x80000000#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000#define INTEGRATOR_HDR1_SDRAM_BASE 0x90000000#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000/* RAM base in reset memory map */#define INTEGRATOR_RESET_RAM_BASE 0x28000000/* PCI Base area */#define INTEGRATOR_PCI_BASE 0x40000000#define INTEGRATOR_PCI_SIZE 0x3FFFFFFF#define BUS BUS_TYPE_PCI/* Signals generated from Integrator clock generator. */#define INTEGRATOR_SYSCLK 20000000 /* System bus clock */#define INTEGRATOR_P_CLK 33000000 /* PCI clock */#define INTEGRATOR_UARTCLK 14745600 /* UART clock */#define INTEGRATOR_CLK24MHZ 24000000 /* KMI/Timer clock *//* Integrator 940T core module registers. */#define INTEGRATOR_HDR_ID_OFFSET 0x00#define INTEGRATOR_HDR_PROC_OFFSET 0x04#define INTEGRATOR_HDR_OSC_OFFSET 0x08#define INTEGRATOR_HDR_CTRL_OFFSET 0x0C#define INTEGRATOR_HDR_STAT_OFFSET 0x10#define INTEGRATOR_HDR_LOCK_OFFSET 0x14#define INTEGRATOR_HDR_SDRAM_OFFSET 0x20#define INTEGRATOR_HDR_INIT_OFFSET 0x24#define INTEGRATOR_HDR_IC_OFFSET 0x40#define INTEGRATOR_HDR_SPDBASE_OFFSET 0x100#define INTEGRATOR_HDR_SPDTOP_OFFSET 0x200#define INTEGRATOR_HDR_CTRL_FASTBUS 0x40#define INTEGRATOR_HDR_BASE 0x10000000#define INTEGRATOR_HDR_ID (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)#define INTEGRATOR_HDR_PROC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)#define INTEGRATOR_HDR_OSC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)#define INTEGRATOR_HDR_CTRL (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)#define INTEGRATOR_HDR_STAT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)#define INTEGRATOR_HDR_LOCK (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)#define INTEGRATOR_HDR_SDRAM (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)#define INTEGRATOR_HDR_INIT (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)#define INTEGRATOR_HDR_IC (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)#define INTEGRATOR_HDR_SPDBASE \ (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)#define INTEGRATOR_HDR_SPDTOP \ (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)#define INTEGRATOR_HDR_OSC_CORE_10MHz (0x102)#define INTEGRATOR_HDR_OSC_CORE_15MHz (0x107)#define INTEGRATOR_HDR_OSC_CORE_20MHz (0x10C)#define INTEGRATOR_HDR_OSC_CORE_25MHz (0x111)#define INTEGRATOR_HDR_OSC_CORE_30MHz (0x116)#define INTEGRATOR_HDR_OSC_CORE_35MHz (0x11B)#define INTEGRATOR_HDR_OSC_CORE_40MHz (0x120)#define INTEGRATOR_HDR_OSC_CORE_45MHz (0x125)#define INTEGRATOR_HDR_OSC_CORE_50MHz (0x12A)#define INTEGRATOR_HDR_OSC_CORE_55MHz (0x12F)#define INTEGRATOR_HDR_OSC_CORE_60MHz (0x134)#define INTEGRATOR_HDR_OSC_CORE_65MHz (0x139)#define INTEGRATOR_HDR_OSC_CORE_70MHz (0x13E)#define INTEGRATOR_HDR_OSC_CORE_75MHz (0x143)#define INTEGRATOR_HDR_OSC_CORE_80MHz (0x148)#define INTEGRATOR_HDR_OSC_CORE_85MHz (0x14D)#define INTEGRATOR_HDR_OSC_CORE_90MHz (0x152)#define INTEGRATOR_HDR_OSC_CORE_95MHz (0x157)#define INTEGRATOR_HDR_OSC_CORE_100MHz (0x15C)#define INTEGRATOR_HDR_OSC_CORE_105MHz (0x161)#define INTEGRATOR_HDR_OSC_CORE_110MHz (0x166)#define INTEGRATOR_HDR_OSC_CORE_115MHz (0x16B)#define INTEGRATOR_HDR_OSC_CORE_120MHz (0x170)#define INTEGRATOR_HDR_OSC_CORE_125MHz (0x175)#define INTEGRATOR_HDR_OSC_CORE_130MHz (0x17A)#define INTEGRATOR_HDR_OSC_CORE_135MHz (0x17F)#define INTEGRATOR_HDR_OSC_CORE_140MHz (0x184)#define INTEGRATOR_HDR_OSC_CORE_145MHz (0x189)#define INTEGRATOR_HDR_OSC_CORE_150MHz (0x18E)#define INTEGRATOR_HDR_OSC_CORE_155MHz (0x193)#define INTEGRATOR_HDR_OSC_CORE_160MHz (0x198)#define INTEGRATOR_HDR_OSC_CORE_MASK (0x7FF)#define INTEGRATOR_HDR_OSC_MEM_10MHz (0x10C000)#define INTEGRATOR_HDR_OSC_MEM_15MHz (0x116000)#define INTEGRATOR_HDR_OSC_MEM_20MHz (0x120000)#define INTEGRATOR_HDR_OSC_MEM_25MHz (0x12A000)#define INTEGRATOR_HDR_OSC_MEM_30MHz (0x134000)#define INTEGRATOR_HDR_OSC_MEM_33MHz (0x13A000)#define INTEGRATOR_HDR_OSC_MEM_40MHz (0x148000)#define INTEGRATOR_HDR_OSC_MEM_50MHz (0x15C000)#define INTEGRATOR_HDR_OSC_MEM_60MHz (0x170000)#define INTEGRATOR_HDR_OSC_MEM_66MHz (0x17C000)#define INTEGRATOR_HDR_OSC_MEM_MASK (0x7FF000)/* * Values we use for core and memory clocks on different header cards. Later * versions of cards and/or upgraded FPGAs on the boards may enable the cards * to run at faster speeds. * * These are: * * Processor Core Memory Bus System Bus PCI Bus * ========= ==== ========== ========== ======= * Unknown 40MHz 20MHz 20MHz 33MHz * ARM720T 50MHz 40MHz 20MHz 33MHz * ARM740T 50MHz 40MHz 20MHz 33MHz * ARM920T 140MHz 25MHz 20MHz 33MHz * ARM940T 100MHz 25MHz 20MHz 33MHz * ARM946ES 100MHz 25MHz 20MHz 33MHz * ARM966ES 120MHz 40MHz 20MHz 33MHz * * NOTE * ==== * The memory bus frequency of 25 MHz for ARM 9 cores is a very * conservative figure. Depending on silicon manufacturer and version, it may * be possible to select a higher frequency by experimentation. */#define INTEGRATOR_HDR_OSC_DFLT_VAL \ (INTEGRATOR_HDR_OSC_CORE_40MHz | INTEGRATOR_HDR_OSC_MEM_20MHz)#define INTEGRATOR_HDR_OSC_720T_VAL \ (INTEGRATOR_HDR_OSC_CORE_50MHz | INTEGRATOR_HDR_OSC_MEM_40MHz)#define INTEGRATOR_HDR_OSC_740T_VAL \ (INTEGRATOR_HDR_OSC_CORE_50MHz | INTEGRATOR_HDR_OSC_MEM_25MHz)#define INTEGRATOR_HDR_OSC_920T_VAL \ (INTEGRATOR_HDR_OSC_CORE_140MHz | INTEGRATOR_HDR_OSC_MEM_25MHz)#define INTEGRATOR_HDR_OSC_940T_VAL \ (INTEGRATOR_HDR_OSC_CORE_100MHz | INTEGRATOR_HDR_OSC_MEM_25MHz)#define INTEGRATOR_HDR_OSC_946ES_VAL \ (INTEGRATOR_HDR_OSC_CORE_80MHz | INTEGRATOR_HDR_OSC_MEM_25MHz)#define INTEGRATOR_HDR_OSC_966ES_VAL INTEGRATOR_HDR_OSC_CORE_120MHz#define INTEGRATOR_HDR_REMAP 0x4#define INTEGRATOR_HDR_SDRAM_SPD_OK 0x20#define INTEGRATOR_HDR_PLLBYPASS_ON 0x3#define INTEGRATOR_HDR_HCLKDIV_3 0x20#define INTEGRATOR_HDR_CLKRATIO_2 0x100#define INTEGRATOR_HDR_TCRAM_ENABLE 0x10000#define INTEGRATOR_HDR_TCRAM_EMULATE 0x20000/* Integrator EBI register definitions. */#define INTEGRATOR_EBI_BASE 0x12000000#define INTEGRATOR_EBI_CSR0_OFFSET 0x00#define INTEGRATOR_EBI_CSR1_OFFSET 0x04#define INTEGRATOR_EBI_CSR2_OFFSET 0x08#define INTEGRATOR_EBI_CSR3_OFFSET 0x0C#define INTEGRATOR_EBI_LOCK_OFFSET 0x20#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)#define INTEGRATOR_EBI_8_BIT 0x00#define INTEGRATOR_EBI_16_BIT 0x01#define INTEGRATOR_EBI_32_BIT 0x02#define INTEGRATOR_EBI_WRITE_ENABLE 0x04#define INTEGRATOR_EBI_SYNC 0x08#define INTEGRATOR_EBI_WS_2 0x00#define INTEGRATOR_EBI_WS_3 0x10#define INTEGRATOR_EBI_WS_4 0x20#define INTEGRATOR_EBI_WS_5 0x30#define INTEGRATOR_EBI_WS_6 0x40#define INTEGRATOR_EBI_WS_7 0x50#define INTEGRATOR_EBI_WS_8 0x60#define INTEGRATOR_EBI_WS_9 0x70#define INTEGRATOR_EBI_WS_10 0x80#define INTEGRATOR_EBI_WS_11 0x90#define INTEGRATOR_EBI_WS_12 0xA0#define INTEGRATOR_EBI_WS_13 0xB0#define INTEGRATOR_EBI_WS_14 0xC0#define INTEGRATOR_EBI_WS_15 0xD0#define INTEGRATOR_EBI_WS_16 0xE0#define INTEGRATOR_EBI_WS_17 0xF0/* System Controller */#define INTEGRATOR_SC_ID_OFFSET (0x00)#define INTEGRATOR_SC_OSC_OFFSET (0x04)#define INTEGRATOR_SC_CTRLS_OFFSET (0x08)#define INTEGRATOR_SC_CTRLC_OFFSET (0x0C)#define INTEGRATOR_SC_DEC_OFFSET (0x10)#define INTEGRATOR_SC_ARB_OFFSET (0x14)#define INTEGRATOR_SC_PCIENABLE_OFFSET (0x18)#define INTEGRATOR_SC_LOCK_OFFSET (0x1C)#define INTEGRATOR_SC_BASE (0x11000000)#define INTEGRATOR_SC_ID \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)#define INTEGRATOR_SC_OSC \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)#define INTEGRATOR_SC_CTRLS \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)#define INTEGRATOR_SC_CTRLC \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)#define INTEGRATOR_SC_DEC \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)#define INTEGRATOR_SC_ARB \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)#define INTEGRATOR_SC_PCIENABLE \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)#define INTEGRATOR_SC_LOCK \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)#define INTEGRATOR_SC_OSC_SYS_10MHz (0x20)#define INTEGRATOR_SC_OSC_SYS_15MHz (0x34)#define INTEGRATOR_SC_OSC_SYS_20MHz (0x48)#define INTEGRATOR_SC_OSC_SYS_25MHz (0x5C)#define INTEGRATOR_SC_OSC_SYS_33MHz (0x7C)#define INTEGRATOR_SC_OSC_SYS_MASK (0xFF)#define INTEGRATOR_SC_OSC_PCI_25MHz (0x100)#define INTEGRATOR_SC_OSC_PCI_33MHz (0x0)#define INTEGRATOR_SC_OSC_PCI_MASK (0x100)#define FL_SC_CONTROL 0x06 /* Enable Flash Write and Vpp *//* - Hard coded id of the core module we are compiling for. */#define CORE_MODULE 0/* * interrupt control stuff * Note: FIQ is not handled within VxWorks so this is just IRQ */#define IC_BASE (0x14000000 + (CORE_MODULE * 0x40))#define IRQ_STATUS (IC_BASE+0x000) /* Read */#define IRQ_RAW_STATUS (IC_BASE+0x004) /* Read */#define IRQ_ENABLE (IC_BASE+0x008) /* Read/Write */#define IRQ_DISABLE (IC_BASE+0x00C) /* Write */#define IRQ_SOFT (IC_BASE+0x010) /* Read/Write */#define IRQ_SOFTCLR (IC_BASE+0x014) /* Write */#define FIQ_STATUS (IC_BASE+0x020) /* Read */#define FIQ_RAW_STATUS (IC_BASE+0x024) /* Read */#define FIQ_ENABLE (IC_BASE+0x028) /* Read/Write */#define FIQ_DISABLE (IC_BASE+0x02C) /* Write */#define AMBA_INT_NUM_LEVELS 22#define AMBA_INT_CSR_PEND IRQ_STATUS#define AMBA_INT_CSR_ENB IRQ_ENABLE#define AMBA_INT_CSR_DIS IRQ_DISABLE#define AMBA_INT_CSR_MASK 0x003FFFFF /* Mask out invalid status bits *//* Interrupt levels */#define INT_LVL_SOFT 0 /* soft interrupt */#define INT_LVL_UART_0 1 /* UART 0 */#define INT_LVL_UART_1 2 /* UART 1 */#define INT_LVL_KEYBOARD 3 /* keyboard interrupt */#define INT_LVL_MOUSE 4 /* mouse interrupt */#define INT_LVL_TIMER_0 5 /* timer 0 */#define INT_LVL_TIMER_1 6 /* timer 1 */#define INT_LVL_TIMER_2 7 /* timer 2 */#define INT_LVL_RTC 8 /* real-time clock */#define INT_LVL_EXP0 9 /* logic module 0 */#define INT_LVL_EXP1 10 /* logic module 1 */#define INT_LVL_EXP2 11 /* logic module 2 */#define INT_LVL_EXP3 12 /* logic module 3 */⌨️ 快捷键说明
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