📄 rtxconf.a51
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INT_ENTRY 12
INT_ENTRY 13
INT_ENTRY 16
INT_ENTRY 18
INT_ENTRY 19
INT_ENTRY 20
INT_ENTRY 21
ELSEIF (?RTX_SYSTEM_TIMER = 2)
; Do NOT include the Timer 2 Vector (INT-5)
INT_ENTRY 0
INT_ENTRY 1
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
INT_ENTRY 8
INT_ENTRY 9
INT_ENTRY 10
INT_ENTRY 11
INT_ENTRY 12
INT_ENTRY 13
INT_ENTRY 16
INT_ENTRY 18
INT_ENTRY 19
INT_ENTRY 20
INT_ENTRY 21
ENDIF
;------------------------------------------------------------------
; The following table attaches the interrupt numbers (0..31) to the
; corresponding bits in the interrupt enable masks of the specific
; processor.
; All three interrupt enable register contents must be defined
; for every interrupt number (even when the specific processor contains
; only one interrupt mask).
; Syntax: DB IE-content, IE1-content, IE2-content
;
?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
?RTX_INT_TO_BIT_TABLE_BASE:
DB 01H, 00H, 00H ; INT_0 (P3.2/INT0)
DB 02H, 00H, 00H ; INT_1 (Timer 0)
DB 04H, 00H, 00H ; INT_2 (P3.3/INT1)
DB 08H, 00H, 00H ; INT_3 (Timer 1)
DB 10H, 00H, 00H ; INT_4 (Ser. channel 0)
DB 20H, 00H, 00H ; INT_5 (Timer 2/ ext. reload)
DB 00H, 00H, 00H ; INT_6 not used
DB 00H, 00H, 00H ; INT_7 not used
DB 00H, 01H, 00H ; INT_8 (A/D-Converter)
DB 00H, 02H, 00H ; INT_9 (P1.4/INT2/CC4)
DB 00H, 04H, 00H ; INT_10 (P1.0/INT3/CC0)
DB 00H, 08H, 00H ; INT_11 (P1.1/INT4/CC1)
DB 00H, 10H, 00H ; INT_12 (P1.2/INT5/CC2)
DB 00H, 20H, 00H ; INT_13 (P1.3/INT6/CC3)
DB 00H, 00H, 00H ; INT_14 not used
DB 00H, 00H, 00H ; INT_15 not used
DB 00H, 00H, 01H ; INT_16 (Serial Channel 1)
DB 00H, 00H, 00H ; INT_17 not used
DB 00H, 00H, 04H ; INT_18 (Match in CM0-CM7)
DB 00H, 00H, 08H ; INT_19 (Compare timer ov.)
DB 00H, 00H, 10H ; INT_20 (Match in COMSET)
DB 00H, 00H, 20H ; INT_21 (Match in COMCLR)
;------------------------------------------------------------------
; Define the greatest supported interrupt number
?RTX_MAX_INT_NBR EQU 21
PCON DATA 87H
ENTER_IDLE MACRO
;;
;; Enter Idle Mode
;; ---------------
;; To be used whenever entering idle state.
;;
ORL PCON, #01H ; Set idle mode (leave by interrupt)
ORL PCON, #20H ; (peripherals stay active)
ENDM
ELSEIF (?RTX_CPU_TYPE = 10)
;***********
;* Type 10 *
;***********
;------------------------------------------------------------------
; Define the number and addresses of the interrupt enable registers
; 80652 -> 1 interrupt enable register
; (Set the not used registers to the same address as ?RTX_IE)
INT_EN_MASK_NUMBER EQU 1
?RTX_IE DATA 0A8H
?RTX_IEN1 DATA 0A8H ; not used
?RTX_IEN2 DATA 0A8H ; not used
;------------------------------------------------------------------
; Generate the interrupt entry points supported by the peripherals
; of the selected CPU type.
IF (?RTX_SYSTEM_TIMER = 0)
; Do NOT include the Timer 0 Vector (INT-1)
INT_ENTRY 0
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
INT_ENTRY 5
ELSEIF (?RTX_SYSTEM_TIMER = 1)
; Do NOT include the Timer 1 Vector (INT-3)
INT_ENTRY 0
INT_ENTRY 1
INT_ENTRY 2
INT_ENTRY 4
INT_ENTRY 5
ENDIF
;------------------------------------------------------------------
; The following table attaches the interrupt numbers (0..31) to the
; corresponding bits in the interrupt enable masks of the specific
; processor.
; All three interrupt enable register contents must be defined
; for every interrupt number (even when the specific processor contains
; only one interrupt mask).
; Syntax: DB IE-content, IE1-content, IE2-content
;
?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
?RTX_INT_TO_BIT_TABLE_BASE:
DB 01H, 00H, 00H ; INT_0 (P3.2/INT0)
DB 02H, 00H, 00H ; INT_1 (Timer 0)
DB 04H, 00H, 00H ; INT_2 (P3.3/INT1)
DB 08H, 00H, 00H ; INT_3 (Timer 1)
DB 10H, 00H, 00H ; INT_4 (Ser. channel 0)
DB 20H, 00H, 00H ; INT_5 (Ser. channel 1)
;------------------------------------------------------------------
; Define the greatest supported interrupt number
?RTX_MAX_INT_NBR EQU 5
PCON DATA 87H
ENTER_IDLE MACRO
;;
;; Enter Idle Mode
;; ---------------
;; Not supported by all 8051 type processors (see manufacturer's
;; data sheet !)
;; To be used whenever entering idle state.
;;
ORL PCON, #01H ; Set idle mode (leave by interrupt)
; (peripherals stay active)
ENDM
ELSEIF (?RTX_CPU_TYPE = 11)
;***********
;* Type 11 *
;***********
;------------------------------------------------------------------
; Define the number and addresses of the interrupt enable registers
; 80410/610 -> 2 interrupt enable registers
; (Set the not used registers to the same address as ?RTX_IE)
INT_EN_MASK_NUMBER EQU 2
?RTX_IE DATA 0A8H
?RTX_IEN1 DATA 0E8H
?RTX_IEN2 DATA 0A8H ; not used
;------------------------------------------------------------------
; Generate the interrupt entry points supported by the peripherals
; of the selected CPU type.
IF (?RTX_SYSTEM_TIMER = 0)
; Do NOT include the Timer 0 Vector (INT-1)
INT_ENTRY 0
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 5
INT_ENTRY 7
INT_ENTRY 8
INT_ENTRY 9
INT_ENTRY 10
INT_ENTRY 11
INT_ENTRY 12
INT_ENTRY 13
INT_ENTRY 14
ELSEIF (?RTX_SYSTEM_TIMER = 1)
; Do NOT include the Timer 1 Vector (INT-3)
INT_ENTRY 0
INT_ENTRY 1
INT_ENTRY 2
INT_ENTRY 5
INT_ENTRY 7
INT_ENTRY 8
INT_ENTRY 9
INT_ENTRY 10
INT_ENTRY 11
INT_ENTRY 12
INT_ENTRY 13
INT_ENTRY 14
ENDIF
;------------------------------------------------------------------
; The following table attaches the interrupt numbers (0..31) to the
; corresponding bits in the interrupt enable masks of the specific
; processor.
; All three interrupt enable register contents must be defined
; for every interrupt number (even when the specific processor contains
; only one interrupt mask).
; Syntax: DB IE-content, IE1-content, IE2-content
;
?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
?RTX_INT_TO_BIT_TABLE_BASE:
DB 01H, 00H, 00H ; INT_0 (INT0)
DB 02H, 00H, 00H ; INT_1 (Timer 0)
DB 04H, 00H, 00H ; INT_2 (INT1)
DB 08H, 00H, 00H ; INT_3 (Timer 1)
DB 00H, 00H, 00H ; INT_4 not used
DB 20H, 00H, 00H ; INT_5 (I2C)
DB 00H, 00H, 00H ; INT_6 not used
DB 00H, 01H, 00H ; INT_7 (INT2)
DB 00H, 02H, 00H ; INT_8 (INT3)
DB 00H, 04H, 00H ; INT_9 (INT4)
DB 00H, 08H, 00H ; INT_10 (INT5)
DB 00H, 10H, 00H ; INT_11 (INT6)
DB 00H, 20H, 00H ; INT_12 (INT7)
DB 00H, 40H, 00H ; INT_13 (INT8)
DB 00H, 80H, 00H ; INT_14 (INT9)
;------------------------------------------------------------------
; Define the greatest supported interrupt number
?RTX_MAX_INT_NBR EQU 14
PCON DATA 87H
ENTER_IDLE MACRO
;;
;; Enter Idle Mode
;; ---------------
;; Not supported by all 8051 type processors (see manufacturer's
;; data sheet !)
;; To be used whenever entering idle state.
;;
ORL PCON, #01H ; Set idle mode (leave by interrupt)
; (peripherals stay active)
ENDM
ELSEIF (?RTX_CPU_TYPE = 12)
;***********
;* Type 12 *
;***********
;------------------------------------------------------------------
; Define the number and addresses of the interrupt enable registers
; 80550 -> 1 interrupt enable register
; (Set the not used registers to the same address as ?RTX_IE)
INT_EN_MASK_NUMBER EQU 1
?RTX_IE DATA 0A8H
?RTX_IEN1 DATA 0A8H ; not used
?RTX_IEN2 DATA 0A8H ; not used
;------------------------------------------------------------------
; Generate the interrupt entry points supported by the peripherals
; of the selected CPU type.
IF (?RTX_SYSTEM_TIMER = 0)
; Do NOT include the Timer 0 Vector (INT-1)
INT_ENTRY 0
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
INT_ENTRY 5
INT_ENTRY 6
ELSEIF (?RTX_SYSTEM_TIMER = 1)
; Do NOT include the Timer 1 Vector (INT-3)
INT_ENTRY 0
INT_ENTRY 1
INT_ENTRY 2
INT_ENTRY 4
INT_ENTRY 5
INT_ENTRY 6
ENDIF
;------------------------------------------------------------------
; The following table attaches the interrupt numbers (0..31) to the
; corresponding bits in the interrupt enable masks of the specific
; processor.
; All three interrupt enable register contents must be defined
; for every interrupt number (even when the specific processor contains
; only one interrupt mask).
; Syntax: DB IE-content, IE1-content, IE2-content
;
?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
?RTX_INT_TO_BIT_TABLE_BASE:
DB 01H, 00H, 00H ; INT_0 (INT0)
DB 02H, 00H, 00H ; INT_1 (Timer 0)
DB 04H, 00H, 00H ; INT_2 (INT1)
DB 08H, 00H, 00H ; INT_3 (Timer 1)
DB 10H, 00H, 00H ; INT_4 (Ser. channel)
DB 20H, 00H, 00H ; INT_5 (A/D-Converter)
DB 40H, 00H, 00H ; INT_6 (Watchdog-Timer)
;------------------------------------------------------------------
; Define the greatest supported interrupt number
?RTX_MAX_INT_NBR EQU 6
PCON DATA 87H
ENTER_IDLE MACRO
;;
;; Enter Idle Mode
;; ---------------
;; Not supported by all 8051 type processors (see manufacturer's
;; data sheet !)
;; To be used whenever entering idle state.
;;
ORL PCON, #01H ; Set idle mode (leave by interrupt)
; (peripherals stay active)
ENDM
ELSEIF (?RTX_CPU_TYPE = 13)
;***********
;* Type 13 *
;***********
;------------------------------------------------------------------
; Define the number and addresses of the interrupt enable registers
; 8051GB -> 2 interrupt enable registers
; (Set the not used registers to the same address as ?RTX_IE)
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