📄 rtxconf.a51
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$TITLE ('RTX-51 CONFIGURATION')
$SYMBOLS
$NOXREF
$NOCOND
$NOMOD51
$NORB
$PAGELENGTH(80) PAGEWIDTH(110)
;************************************************************************
;* *
;* R T X - 5 1 : Configuration data for RTX-51 V 5.x *
;* *
;*----------------------------------------------------------------------*
;* *
;* Filename : RTXCONF.A51 *
;* Language : Keil A-51 *
;* Dev. system : IBM PC *
;* Targetsystem : Any system based upon 8051 up *
;* *
;* Date: 9-MAY-1996 *
;* *
;* Purpose : - Defines the processor specific data *
;* definitions for all supported processors. *
;* New processor types may be easily added. *
;* - Defines all user configurable system values. *
;* *
;*----------------------------------------------------------------------*
;* Rev. | Released | Programmer | Comments *
;*----------------------------------------------------------------------*
;* 0.1 | 4-APR-1991 | ThF | First Version *
;* 5.00 | 3-NOV-1994 | EG | Release V 5.00 *
;* 5.01 | 7-SEP-1995 | | Avoid L51 msg "empty segments", *
;* | | | few INT_EN_MASK_NUMBER's corrected*
;* 5.10 | 9-MAY-1996 | | T2 support for CPU=2,5,13,14,16,17*
;* | | | Add ?RTX_IDLE_FUNC *
;* 5.10 | 26-MAY-1997 | | Type 21(C515C) implemented *
;************************************************************************
;* (c) METTLER & FUCHS AG, LOEWENSTRASSE 21, CH-8953 Dietikon *
;* Tel. (+41) (1) 740 41 00 / Fax (+41) (1) 740 15 67 *
;************************************************************************
;*----------------------------------------------------------------------*
;*
;* USER CONFIGURABLE SYSTEM VALUES
;*
;* All configurable values are contained in include file RTXSETUP.DCL
;* (for details see the program documentation).
;*----------------------------------------------------------------------*
$INCLUDE(RTXSETUP.DCL)
;========================================================================
; END OF USER-CONFIGURABLE SECTION
;========================================================================
$EJECT
;************************************************************************
;* *
;* THE FOLLOWING SECTIONS MUST NORMALLY NOT BE ALTERED BY THE USER *
;* --------------------------------------------------------------- *
;* *
;************************************************************************
NAME ?RTX?CONFIGURATION ; Do NOT alter the modulename !
;*----------------------------------------------------------------------*
;* IMPORTS
;*----------------------------------------------------------------------*
EXTRN BIT (?RTX_ENA_INT_REG1, ?RTX_ENA_INT_REG2) ; from RTXDATA
EXTRN CODE (?RTX_SYSCLK_INTHNDLR) ; from RTXCLK
EXTRN CODE (?RTX_INT_HANDLER) ; from RTXINT
EXTRN DATA (?RTX_TMP1) ; from RTXDATA
IF (?RTX_BANKSWITCHING = 1)
EXTRN DATA (?B_CURRENTBANK) ; from L51_BANK
EXTRN NUMBER (?B_MASK, ?B_FACTOR) ; from L51_BANK
EXTRN CODE (_SWITCHBANK) ; from L51_BANK
ENDIF
;*----------------------------------------------------------------------*
;* EXPORTS
;*----------------------------------------------------------------------*
; System constants
PUBLIC ?RTX_EXTRENTSIZE, ?RTX_EXTSTKSIZE, ?RTX_INTSTKSIZE
PUBLIC ?RTX_TIMESHARING, ?RTX_BANKSWITCHING, ?RTX_INTREGSIZE
PUBLIC ?RTX_MAILBOX_SUPPORT, ?RTX_SEMAPHORE_SUPPORT
; Initial Interrupt mask values
PUBLIC ?RTX_IE_INIT, ?RTX_IEN1_INIT, ?RTX_IEN2_INIT
; Enable the interrupt enable registers for the selected processor
PUBLIC ?RTX_INIT_INT_REG_FLAGS
; Interrupt number to enable-mask table
PUBLIC ?RTX_INT_TO_BIT_TABLE_BASE
; Greatest interrupt number
PUBLIC ?RTX_MAX_INT_NBR
; Processor specific interrupt enable masks
PUBLIC ?RTX_IE, ?RTX_IEN1, ?RTX_IEN2
; Interrupt mask variables
PUBLIC ?RTX_NM_IE, ?RTX_D_IE, ?RTX_ND_IE
PUBLIC ?RTX_NM_IE1, ?RTX_D_IE1, ?RTX_ND_IE1
PUBLIC ?RTX_NM_IE2, ?RTX_D_IE2, ?RTX_ND_IE2
; System Timer constants
PUBLIC ?RTX_CLK_INT_NBR ; EQUATE
PUBLIC ?RTX_TLOW, ?RTX_THIGH, ?RTX_TMOD ; DATA
PUBLIC ?RTX_TCON ; DATA
PUBLIC ?RTX_TFLAG, ?RTX_TCONTROL ; BIT
PUBLIC ?RTX_TMOD_AND_MASK, ?RTX_TMOD_OR_MASK ; EQUATES
PUBLIC ?RTX_TCON_AND_MASK, ?RTX_TCON_OR_MASK ; EQUATES
; Bank-Switching Support
PUBLIC ?RTX_SWITCHBANK ; CODE
PUBLIC ?RTX_SAVE_INT_BANK ; DATA
IF (?RTX_BANKSWITCHING = 0)
PUBLIC ?B_CURRENTBANK ; Dummy DATA-Definition
ENDIF
; Idle function
PUBLIC ?RTX_IDLE_FUNC
; Mailbox and semaphore FIFO space
PUBLIC ?RTX_MBX_PAGE
PUBLIC ?RTX_MBX_PAGE_END
PUBLIC ?RTX_SEM_PAGE
PUBLIC ?RTX_SEM_PAGE_END
;*----------------------------------------------------------------------*
;* MACROS
;*----------------------------------------------------------------------*
; This MACRO generates an RTX-51 interrupt entry point using the base
; address ?RTX_INTBASE.
INT_ENTRY MACRO NO
EXTRN XDATA (?RTX_INT&NO&_TID)
PUBLIC INT&NO&_VECTOR
CSEG AT(?RTX_INTBASE+3+(&NO&*8))
INT&NO&_VECTOR: MOV ?RTX_TMP1, A ; Save A
MOV A, #LOW(?RTX_INT&NO&_TID); Set up ptr to int. TID
LJMP ?RTX_INT_HANDLER ; Jump to general ISR
ENDM
;*----------------------------------------------------------------------*
;* PROCESSOR SPECIFIC DATA DEFINITIONS
;*----------------------------------------------------------------------*
IF (?RTX_CPU_TYPE = 1)
;***********
;* Type 1 *
;***********
;------------------------------------------------------------------
; Define the number and addresses of the interrupt enable registers
; 8051 -> 1 interrupt enable register
; (Set the not used registers to the same address as ?RTX_IE)
INT_EN_MASK_NUMBER EQU 1
?RTX_IE DATA 0A8H
?RTX_IEN1 DATA 0A8H ; not used
?RTX_IEN2 DATA 0A8H ; not used
;------------------------------------------------------------------
; Generate the interrupt entry points supported by the peripherals
; of the selected CPU type.
IF (?RTX_SYSTEM_TIMER = 0)
; Do NOT include the Timer 0 Vector (INT-1)
INT_ENTRY 0
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
ELSEIF (?RTX_SYSTEM_TIMER = 1)
; Do NOT include the Timer 1 Vector (INT-3)
INT_ENTRY 0
INT_ENTRY 1
INT_ENTRY 2
INT_ENTRY 4
ENDIF
;------------------------------------------------------------------
; The following table attaches the interrupt numbers (0..31) to the
; corresponding bits in the interrupt enable masks of the specific
; processor.
; All three interrupt enable register contents must be defined
; for every interrupt number (even when the specific processor contains
; only one interrupt mask).
; Syntax: DB IE-content, IE1-content, IE2-content
;
?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
?RTX_INT_TO_BIT_TABLE_BASE:
DB 01H, 00H, 00H ; INT_0 (P3.2/INT0)
DB 02H, 00H, 00H ; INT_1 (Timer 0)
DB 04H, 00H, 00H ; INT_2 (P3.3/INT1)
DB 08H, 00H, 00H ; INT_3 (Timer 1)
DB 10H, 00H, 00H ; INT_4 (Ser. channel)
;------------------------------------------------------------------
; Define the greatest supported interrupt number
?RTX_MAX_INT_NBR EQU 4
PCON DATA 87H
ENTER_IDLE MACRO
;;
;; Enter Idle Mode
;; ---------------
;; Not supported by all 8051 type processors (see manufacturer's
;; data sheet !)
;; To be used whenever entering idle state.
;;
ORL PCON, #01H ; Set idle mode (leave by interrupt)
; (peripherals stay active)
ENDM
ELSEIF (?RTX_CPU_TYPE = 2)
;**********
;* Type 2 *
;**********
;------------------------------------------------------------------
; Define the number and addresses of the interrupt enable registers
; 8052 -> 1 interrupt enable register
; (Set the not used registers to the same address as ?RTX_IE)
INT_EN_MASK_NUMBER EQU 1
?RTX_IE DATA 0A8H
?RTX_IEN1 DATA 0A8H ; not used
?RTX_IEN2 DATA 0A8H ; not used
;------------------------------------------------------------------
; Generate the interrupt entry points supported by the peripherals
; of the selected CPU type.
IF (?RTX_SYSTEM_TIMER = 0)
; Do NOT include the Timer 0 Vector (INT-1)
INT_ENTRY 0
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
INT_ENTRY 5
ELSEIF (?RTX_SYSTEM_TIMER = 1)
; Do NOT include the Timer 1 Vector (INT-3)
INT_ENTRY 0
INT_ENTRY 1
INT_ENTRY 2
INT_ENTRY 4
INT_ENTRY 5
ELSEIF (?RTX_SYSTEM_TIMER = 2)
; Do NOT include the Timer 2 Vector (INT-5)
INT_ENTRY 0
INT_ENTRY 1
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
ENDIF
;------------------------------------------------------------------
; The following table attaches the interrupt numbers (0..31) to the
; corresponding bits in the interrupt enable masks of the specific
; processor.
; All three interrupt enable register contents must be defined
; for every interrupt number (even when the specific processor contains
; only one interrupt mask).
; Syntax: DB IE-content, IE1-content, IE2-content
;
?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF SEGMENT CODE
RSEG ?RTX?RTX_INT_TO_BIT_TABLE?RTXCONF
?RTX_INT_TO_BIT_TABLE_BASE:
DB 01H, 00H, 00H ; INT_0 (P3.2/INT0)
DB 02H, 00H, 00H ; INT_1 (Timer 0)
DB 04H, 00H, 00H ; INT_2 (P3.3/INT1)
DB 08H, 00H, 00H ; INT_3 (Timer 1)
DB 10H, 00H, 00H ; INT_4 (Ser. channel)
DB 20H, 00H, 00H ; INT_5 (Timer 2)
;------------------------------------------------------------------
; Define the greatest supported interrupt number
?RTX_MAX_INT_NBR EQU 5
PCON DATA 87H
ENTER_IDLE MACRO
;;
;; Enter Idle Mode
;; ---------------
;; Not supported by all 8052 type processors (see manufacturer's
;; data sheet !)
;; To be used whenever entering idle state.
;;
ORL PCON, #01H ; Set idle mode (leave by interrupt)
; (peripherals stay active)
ENDM
ELSEIF (?RTX_CPU_TYPE = 3)
;**********
;* Type 3 *
;**********
;------------------------------------------------------------------
; Define the number and addresses of the interrupt enable registers
; 80515/535 -> 2 interrupt enable registers
; (Set the not used registers to the same address as ?RTX_IE)
INT_EN_MASK_NUMBER EQU 2
?RTX_IE DATA 0A8H
?RTX_IEN1 DATA 0B8H
?RTX_IEN2 DATA 0A8H ; not used
;------------------------------------------------------------------
; Generate the interrupt entry points supported by the peripherals
; of the selected CPU type.
IF (?RTX_SYSTEM_TIMER = 0)
; Do NOT include the Timer 0 Vector (INT-1)
INT_ENTRY 0
INT_ENTRY 2
INT_ENTRY 3
INT_ENTRY 4
INT_ENTRY 5
INT_ENTRY 8
INT_ENTRY 9
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