📄 start390.lst
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AX51 MACRO ASSEMBLER START390 04/27/04 18:11:32 PAGE 1
MACRO ASSEMBLER AX51 V2.12
OBJECT MODULE PLACED IN START390.OBJ
ASSEMBLER INVOKED BY: C:\Keil\C51\BIN\AX51.EXE START390.A51 MOD_CONT SET(SMALL,MOD_CONT) DEBUG EP
LOC OBJ LINE SOURCE
1 $nomod51
2 ;------------------------------------------------------------------------------
3 ; This file is part of the C51 Compiler package
4 ; Copyright (c) 1988-2001 Keil Elektronik GmbH and Keil Software, Inc.
5 ; Startup code for Dallas 390/5240 CPU, Contigious Mode
6 ;------------------------------------------------------------------------------
7 ; START390.A51: This code is executed after processor reset.
8 ; You may add this file to a uVision2 project.
9 ;
10 ; To translate this file use A51 with the following invocation:
11 ;
12 ; AX51 START390.A51 MOD_CONT
13 ;
14 ; To link the modified STARTUP.OBJ file to your application use the following
15 ; LX51 invocation:
16 ;
17 ; LX51 <your object file list>, START390.OBJ <controls>
18 ;
19 ;------------------------------------------------------------------------------
20 ;
21 ; Chip Specific Options
22 ;
23 ; SA: Extend Stack Address Mode Enable (ACON.2)
0000 24 SA EQU 0 ; 0 = 8051 compatible stack in IDATA memory
25 ; ; 1 = Use 1KB stack in on-chip XDATA space
26 ;
27 ; IDM1, IDM0: Internal Data Memory Configuration Bits (MCON.7, MCON.6)
0000 28 IDM EQU 0 ; 0 = 4KB on-chip SRAM location X:0x00F000 - X:0x00FFFF
29 ; ; 1 = 4KB on-chip SRAM location X:0x000000 - X:0x000FFF
30 ; ; 2 = 4KB on-chip SRAM location X:0x400000 - X:0x400FFF
31 ; ; 3 = 4KB on-chip SRAM location X:0x400000 - X:0x400FFF
32 ; and code memory C:0x400000 - C:0x400FFF
33 ;
34 ; CMA: CAN Data Memory Assignment (MCON.5)
0000 35 CMA EQU 0 ; 0 = CAN0 X:0x00EE00 - X:0x00EEFF, CAN1 X:0x00EF00 - X:0x00EFFF
36 ; 1 = CAN0 X:0x401000 - X:0x4010FF, CAN1 X:0x401100 - X:0x4011FF
37 ;
38 ; PDCE3 .. PDCE0: Program/Data Chip Enable (MCON.3, MCON.2, MCON.1, MCON.0)
39 ; Program/Data Chip Enable selects whether the CEx signal functions as the chip
40 ; enable for external program memory only (PDCE=0), or as a merged chip enable
41 ; for program and data memory (PDCE=1).
0000 42 PDCE3 EQU 0 ; PDCE3=0: standard: RD signal for MOVX
43 ; PDCE3=1: von-Neumann: PSEN signal for MOVX
0000 44 PDCE2 EQU 0 ; PDCE2=0: standard: RD signal for MOVX
45 ; PDCE2=1: von-Neumann: PSEN signal for MOVX
0000 46 PDCE1 EQU 0 ; PDCE1=0: standard: RD signal for MOVX
47 ; PDCE1=1: von-Neumann: PSEN signal for MOVX
0000 48 PDCE0 EQU 0 ; PDCE0=0: standard: RD signal for MOVX
49 ; PDCE0=1: von-Neumann: PSEN signal for MOVX
50
51 ; Port 4 Function Control (P4CNT)
52 ; ===============================
53 ; Port 4 Pin Function (P4CNT.0 .. P4CNT.2)
0007 54 P4PF EQU 7 ; 0 : all pin used as I/O pin (P4.0 - P4.3)
55 ; ; 4 : P4.0 is CE0
56 ; ; 5 : P4.0 is CE0, P4.1 is CE1
57 ; ; 6 : P4.0 is CE0, P4.1 is CE1, P4.2 is CE2
58 ; ; 7 : P4.0 is CE0, P4.1 is CE1, P4.2 is CE2, P4.3 is CE3
AX51 MACRO ASSEMBLER START390 04/27/04 18:11:32 PAGE 2
59 ;
60 ; Program Memory Chip Enable Window Size (P4CNT.5 .. P4CNT.3)
0007 61 PCES EQU 7 ; 0 = 32KB address window (0 - 0x7FFF)
62 ; ; 4 = 128KB address window (0 - 0x1FFFF)
63 ; ; 5 = 256KB address window (0 - 0x3FFFF)
64 ; ; 6 = 512KB address window (0 - 0x7FFFF)
65 ; ; 7 = 1MB address window (0 - 0xFFFFF)
66 ;
67 ; Single CAN Configuration (P4CNT.6)
0000 68 SBCAN EQU 0 ; 1 = connects both CAN receive inputs and outputs to P5.0 and P5.1
69 ; 0 = both CAN interfaces work on their respective I/O pins
70
71 ; Port 5 Function Control (P5CNT)
72 ; ===============================
73 ; Serial Port 1 External Connections (P5CNT.5)
0000 74 SP1EC EQU 0 ; 0 = Serial Port is routed to P1.2/P1.3
75 ; ; 1 = Serial Port is routed to P5.2/P5.3
76 ;
77 ; Can I/O Enable (P5CNT.3 .. P5CNT.4)
0000 78 CX_IO EQU 0 ; 0 = P5.0 - P5.3 used as I/O pins
79 ; ; 1 = P5.2 & P5.3 used as I/O pins, P5.0 & P5.1 used by CAN0
80 ; ; 2 = P5.0 & P5.1 used as I/O pins, P5.2 & P5.3 used by CAN1;
81 ; ; 3 = P5.0 & P5.1 used by CAN0, P5.2 & P5.3 used by CAN1;
82 ;
83 ; Port 5 Pin Function (P5CNT.2 .. P5CNT.0)
0007 84 P5PF EQU 7 ; 0 : all pin used as I/O pin (P4.4,P5.5-P5.7)
85 ; ; 4 : P4.4 is PCE0
86 ; ; 5 : P4.4 is PCE0, P5.5 is PCE1
87 ; ; 6 : P4.4 is PCE0, P5.5 is PCE1, P5.6 is PCE2
88 ; ; 7 : P4.4 is PCE0, P5.5 is PCE1, P5.6 is PCE2, P5.7 is PCE3
89
90 ;
91 ;------------------------------------------------------------------------------
92 ;
93 ; User-defined Power-On Initialization of Memory
94 ;
95 ; With the following EQU statements the initialization of memory
96 ; at processor reset can be defined:
97 ;
98 ; ; the absolute start-address of IDATA memory is always 0
0080 99 IDATALEN EQU 80H ; the length of IDATA memory in bytes.
100 ;
0000 101 XDATASTART EQU 0H ; the absolute start-address of XDATA memory
0000 102 XDATALEN EQU 0H ; the length of XDATA memory in bytes.
103 ;
0000 104 PDATASTART EQU 0H ; the absolute start-address of PDATA memory
0000 105 PDATALEN EQU 0H ; the length of PDATA memory in bytes.
106 ;
107 ; Notes: The IDATA space overlaps physically the DATA and BIT areas of the
108 ; 8051 CPU. At minimum the memory space occupied from the C51
109 ; run-time routines must be set to zero.
110 ;------------------------------------------------------------------------------
111 ;
112 ; Reentrant Stack Initilization
113 ;
114 ; The following EQU statements define the stack pointer for reentrant
115 ; functions and initialized it:
116 ;
117 ; Stack Space for reentrant functions in the SMALL model.
0000 118 IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
0100 119 IBPSTACKTOP EQU 0FFH+1 ; set top of stack to highest location+1.
120 ;
121 ; Stack Space for reentrant functions in the LARGE model.
0000 122 XBPSTACK EQU 0 ; set to 1 if large reentrant is used.
00010000 123 XBPSTACKTOP EQU 0FFFFH+1; set top of stack to highest location+1.
124 ;
AX51 MACRO ASSEMBLER START390 04/27/04 18:11:32 PAGE 3
125 ; Stack Space for reentrant functions in the COMPACT model.
0000 126 PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
00010000 127 PBPSTACKTOP EQU 0FFFFH+1; set top of stack to highest location+1.
128 ;
129 ;------------------------------------------------------------------------------
130 ;
131 ; Page Definition for Using the Compact Model with 64 KByte xdata RAM
132 ;
133 ; The following EQU statements define the xdata page used for pdata
134 ; variables. The EQU PPAGE must conform with the PPAGE control used
135 ; in the linker invocation.
136 ;
0000 137 PPAGEENABLE EQU 0 ; set to 1 if pdata object are used.
0000 138 PPAGE EQU 0 ; define PPAGE number.
139 ;
140 ;------------------------------------------------------------------------------
141
142 ;#include <REG390.H>
+1 143
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0080 +1 155 sfr P4 = 0x80;
0090 +1 156 sfr P1 = 0x90;
00A0 +1 157 sfr P2 = 0xA0;
00B0 +1 158 sfr P3 = 0xB0;
00D0 +1 159 sfr PSW = 0xD0;
00E0 +1 160 sfr ACC = 0xE0;
00F0 +1 161 sfr B = 0xF0;
0081 +1 162 sfr SP = 0x81;
0082 +1 163 sfr DPL = 0x82;
0083 +1 164 sfr DPH = 0x83;
0087 +1 165 sfr PCON = 0x87;
0088 +1 166 sfr TCON = 0x88;
0089 +1 167 sfr TMOD = 0x89;
008A +1 168 sfr TL0 = 0x8A;
008B +1 169 sfr TL1 = 0x8B;
008C +1 170 sfr TH0 = 0x8C;
008D +1 171 sfr TH1 = 0x8D;
00A8 +1 172 sfr IE = 0xA8;
00B8 +1 173 sfr IP = 0xB8;
0098 +1 174 sfr SCON0 = 0x98;
0099 +1 175 sfr SBUF0 = 0x99;
+1 176
+1 177
0084 +1 178 sfr DPL1 = 0x84;
0085 +1 179 sfr DPH1 = 0x85;
0086 +1 180 sfr DPS = 0x86;
008E +1 181 sfr CKCON = 0x8E;
0091 +1 182 sfr EXIF = 0x91;
0092 +1 183 sfr P4CNT = 0x92;
0093 +1 184 sfr DPX = 0x93;
0095 +1 185 sfr DPX1 = 0x95;
0096 +1 186 sfr C0RMS0 = 0x96;
0097 +1 187 sfr C0RMS1 = 0x97;
009B +1 188 sfr ESP = 0x9B;
009C +1 189 sfr AP = 0x9C;
009D +1 190 sfr ACON = 0x9D;
AX51 MACRO ASSEMBLER START390 04/27/04 18:11:32 PAGE 4
009E +1 191 sfr C0TMA0 = 0x9E;
009F +1 192 sfr C0TMA1 = 0x9F;
00A1 +1 193 sfr P5 = 0xA1;
00A2 +1 194 sfr P5CNT = 0xA2;
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