44binitbackup.s
来自「ARM-s3c44b0_B2开发板通用非向量IRQ中断的实现.」· S 代码 · 共 563 行 · 第 1/2 页
S
563 行
ldr r0,=HandleTIMER0
ldr r1,=isr_TIMER0
str r1,[r0]
ldr r0,=HandleUERR01
ldr r1,=isr_UERR01
str r1,[r0]
ldr r0,=HandleWDT
ldr r1,=isr_WDT
str r1,[r0]
ldr r0,=HandleBDMA1
ldr r1,=isr_BDMA1
str r1,[r0]
ldr r0,=HandleBDMA0
ldr r1,=isr_BDMA0
str r1,[r0]
ldr r0,=HandleZDMA1
ldr r1,=isr_ZDMA1
str r1,[r0]
ldr r0,=HandleZDMA0
ldr r1,=isr_ZDMA0
str r1,[r0]
ldr r0,=HandleTICK
ldr r1,=isr_TICK
str r1,[r0]
ldr r0,=HandleEINT4567
ldr r1,=isr_EXINT4567
str r1,[r0]
ldr r0,=HandleEINT3
ldr r1,=isr_EXINT3
str r1,[r0]
ldr r0,=HandleEINT2
ldr r1,=isr_EXINT2
str r1,[r0]
ldr r0,=HandleEINT1
ldr r1,=isr_EXINT1
str r1,[r0]
ldr r0,=HandleEINT0
ldr r1,=isr_EXINT0
str r1,[r0]
ldr r0,=HandleSWI
ldr r1,=isr_SWI
str r1,[r0]
;****************************************************
;Copy and paste RW data/zero initialized data *
;****************************************************
LDR r0, =|Image$$RO$$Limit| ; Get pointer to ROM data,r1中存放RO段的起始地址
LDR r1, =|Image$$RW$$Base| ; r1中存放RW段的起始地址
LDR r3, =|Image$$ZI$$Base| ; r3中存放ZI段的起始地址
;Zero init base => top of initialised data
CMP r0, r1 ; Check that they are different
BEQ %F1
0
CMP r1, r3 ; Copy init data,RO段的内容拷贝到RW段中
LDRCC r2, [r0], #4 ;--> LDRCC r2, [r0] , ADD r0, r0, #4,如果r1<r3
STRCC r2, [r1], #4 ;--> STRCC r2, [r1] , ADD r1, r1, #4,如果r1<r3
BCC %B0
1
LDR r1, =|Image$$ZI$$Limit| ; Top of zero init segment
MOV r2, #0
2
CMP r3, r1 ;Zero init
STRCC r2, [r3], #4 ;--> STRCC r2, [r3] , ADD r3, r3, #4,如果r1<r3
BCC %B2
[ :LNOT:THUMBCODE
bl Main ;Don't use main() because ......
b .
]
[ THUMBCODE ;for start-up code for Thumb mode
orr lr,pc,#1
bx lr
CODE16
bl Main ;Don't use main() because ......
b .
CODE32
]
;****************************************************
;* The function for initializing stack *
;****************************************************
InitStacks
;Don't use DRAM,such as stmfd,ldmfd......
;SVCstack is initialized before
;Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
;USERStack # 256 ;c7ff800--0xc7ff8ff ;"#"与FIELD同义，用来定义一个结构化内存表中的数据域
;FIQStack # 256 ;c7ff900--0xc7ff9ff
;IRQStack # 256 ;c7ffa00--0xc7ffaff
;SVCStack # 256 ;c7ffb00--0xc7ffbff ;
;ABTStack # 256 ;c7ffc00--0xc7ffcff
;UNDStack # 256 ;c7ffd00--0xc7ffdff
;SYSStack # 256 ;c7ffe00--0xc7ffeff
mrs r0,cpsr
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#IRQMODE|NOINT
msr cpsr_c,r1 ;IRQMode
ldr sp,=IRQStack+256
mrs r0,cpsr
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#FIQMODE|NOINT
msr cpsr_c,r1 ;FIQMode
ldr sp,=FIQStack+256
mrs r0,cpsr
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#UNDMODE|NOINT
msr cpsr_c,r1 ;UndefMode
ldr sp,=UNDStack+256
mrs r0,cpsr
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#ABTMODE|NOINT
msr cpsr_cxsf,r1 ;AbortMode
ldr sp,=ABTStack+256
; mrs r0,cpsr
; bic r0,r0,#MODEMASK|NOINT
; orr r1,r0,#SYSMODE|NOINT
; msr cpsr_cxsf,r1 ;SYSMODE
; ldr sp,=SVCStack+256
mrs r0,cpsr
bic r0,r0,#MODEMASK|NOINT
orr r1,r0,#SVCMODE|NOINT
msr cpsr_cxsf,r1 ;SVCMode
ldr sp,=SVCStack+256
mov pc,lr ;The LR register may be not valid for the mode changes.
;****************************************************
;* The function for entering power down mode *
;****************************************************
EXPORT initFIQ
initFIQ
mrs r0, cpsr
and r0, r0,#0xbf
msr cpsr_cxsf, r0
MOV PC,LR
;*********************************************
EXPORT initIRQ
initIRQ
mrs r0, cpsr
and r0, r0,#0x7f
msr cpsr_cxsf, r0
MOV PC,LR
;void EnterPWDN(int CLKCON);
;*********************************************
EXPORT EnterPWDN
EnterPWDN
mov r2,r0 ;r0=CLKCON
ldr r0,=REFRESH
ldr r3,[r0]
mov r1, r3
orr r1, r1, #0x400000 ;self-refresh enable
str r1, [r0]
nop ;Wait until self-refresh is issued. May not be needed.
nop ;If the other bus master holds the bus, ...
nop ; mov r0, r0
nop
nop
nop
nop
;enter POWERDN mode
ldr r0,=CLKCON
str r2,[r0]
;wait until enter SL_IDLE,STOP mode and until wake-up
mov r0,#0xff
0 subs r0,r0,#1
bne %B0
;exit from DRAM/SDRAM self refresh mode.
ldr r0,=REFRESH
str r3,[r0]
mov pc,lr
LTORG
;----------------------------------------------------------------------
SMRDATA DATA
;*****************************************************************
;* Memory configuration has to be optimized for best performance *
;* The following parameter is not optimized. *
;*****************************************************************
;*** memory access cycle parameter strategy ***
; 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
; 2) The memory settings,here, are made the safe parameters even at 66Mhz.
; 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
; 4) DRAM refresh rate is for 40Mhz.
[ BUSWIDTH=16
DCD 0x11111001 ;Bank0=OM[1:0], Bank1~Bank7=16bit
| ;BUSWIDTH=32
DCD 0x22222220 ;Bank0=OM[1:0], Bank1~Bank7=32bit
]
DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) ;GCS0
DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) ;GCS1
DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) ;GCS2
DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) ;GCS3
DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) ;GCS4
DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) ;GCS5
[ BDRAMTYPE="DRAM"
DCD ((B6_MT<<15)+(B6_Trcd<<4)+(B6_Tcas<<3)+(B6_Tcp<<2)+(B6_CAN)) ;GCS6 check the MT value in parameter.a
DCD ((B7_MT<<15)+(B7_Trcd<<4)+(B7_Tcas<<3)+(B7_Tcp<<2)+(B7_CAN)) ;GCS7
| ;"SDRAM"
DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) ;GCS6
DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) ;GCS7
]
DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) ;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
DCD 0x10 ;SCLK power down mode, BANKSIZE 32M/32M
DCD 0x20 ;MRSR6 CL=2clk
DCD 0x20 ;MRSR7
ALIGN
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;RW BEGIN;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
AREA RamData, DATA, READWRITE
^ (_ISR_STARTADDRESS-0x700) ;"^"与MAP同义，用来定义一个结构化的内存表中的首地址,_ISR_STARTADDRESS=0xc7fff00,在option.inc中定义
;下面的代码是对内存进行分配
USERStack # 256 ;c7ff800--0xc7ff8ff ;"#"与FIELD同义，用来定义一个结构化内存表中的数据域
FIQStack # 256 ;c7ff900--0xc7ff9ff
IRQStack # 256 ;c7ffa00--0xc7ffaff
SVCStack # 256 ;c7ffb00--0xc7ffbff ;
ABTStack # 256 ;c7ffc00--0xc7ffcff
UNDStack # 256 ;c7ffd00--0xc7ffdff
SYSStack # 256 ;c7ffe00--0xc7ffeff
;一下程序用来在ram中存储44B0的所有中断服务函数的地址，0xc7fff00--0xc7fffff,这段空间总共可存储64个地址
^ _ISR_STARTADDRESS
;为每个地址保留4字节数据域,
HandleADC # 4 ;0xc7fff00--0xc7fff03
HandleRTC # 4 ;0xc7fff04--0xc7fff07
HandleUTXD1 # 4 ;0xc7fff08--0xc7fff0b
HandleUTXD0 # 4 ;0xc7fff0c--0xc7fff0f
HandleSIO # 4 ;0xc7fff10--0xc7fff13
HandleIIC # 4 ;0xc7fff14--0xc7fff17
HandleURXD1 # 4 ;0xc7fff18--0xc7fff1b
HandleURXD0 # 4 ;0xc7fff1c--0xc7fff1f
HandleTIMER5 # 4 ;0xc7fff20--0xc7fff23
HandleTIMER4 # 4 ;0xc7fff24--0xc7fff17
HandleTIMER3 # 4 ;0xc7fff28--0xc7fff2b
HandleTIMER2 # 4 ;0xc7fff2c--0xc7fff2f
HandleTIMER1 # 4 ;0xc7fff30--0xc7fff33
HandleTIMER0 # 4 ;0xc7fff34--0xc7fff37
HandleUERR01 # 4 ;0xc7fff38--0xc7fff3b
HandleWDT # 4 ;0xc7fff3c--0xc7fff3f
HandleBDMA1 # 4 ;0xc7fff40--0xc7fff43
HandleBDMA0 # 4 ;0xc7fff44--0xc7fff47
HandleZDMA1 # 4 ;0xc7fff48--0xc7fff4b
HandleZDMA0 # 4 ;0xc7fff4c--0xc7fff4f
HandleTICK # 4 ;0xc7fff50--0xc7fff53
HandleEINT4567 # 4 ;0xc7fff54--0xc7fff57
HandleEINT3 # 4 ;0xc7fff58--0xc7fff5b
HandleEINT2 # 4 ;0xc7fff5c--0xc7fff5f
HandleEINT1 # 4 ;0xc7fff60--0xc7fff63
HandleEINT0 # 4 ;0xc7fff64--0xc7fff67
HandleSWI # 4 ;0xc7fff68--0xc7fff6c
END
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