📄 xlli_mainstone_defs.inc
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@*********************************************************************************@@ COPYRIGHT (c) 2002 - 2004 Intel Corporation@@ The information in this file is furnished for informational use only,@ is subject to change without notice, and should not be construed as@ a commitment by Intel Corporation. Intel Corporation assumes no@ responsibility or liability for any errors or inaccuracies that may appear@ in this document or any software that may be provided in association with@ this document.@@*********************************************************************************@@ FILENAME: xlli_Mainstone_defs.inc (Platform specific addresses and@ defalut values for Mainstone II platform bring up)@ NOTE: - This file has a def to configure xlli for MCP and non-MCP processors@@ LAST MODIFIED: 13-Feb-2004@@******************************************************************************@@@ Include file for Mainstone II specific Cross Platform Low Level Initialization (XLLI)@@@ Uncomment this line to configure for a Bulverde/MCP build@@.equ xlli_MCP,0@@ PLATFORM REGISTERS base address and register offsets from the base address@ .equ xlli_PLATFORM_REGISTERS,0x08000000 .equ xlli_PLATFORM_HEXLED_DATA_offset,(0x10) @ Hex LED Data Register .equ xlli_PLATFORM_LED_CONTROL_offset,(0x40) @ LED Control Register .equ xlli_PLATFORM_SWITCH_offset,(0x60) @ General Purpose Switch Register .equ xlli_PLATFORM_MISC_WRITE1_offset,(0x80) @ Misc Write Register 1 .equ xlli_PLATFORM_MISC_WRITE2_offset,(0x84) @ Misc Write Register 2 .equ xlli_PLATFORM_MISC_READ1_offset,(0x90) @ Misc Read Register 1 .equ xlli_PLATFORM_INTERR_ME_offset,(0xC0) @ Platform Interrupt Mask/Enable Register 1 .equ xlli_PLATFORM_INTERR_SC_offset,(0xD0) @ Platform Interrupt Set/Clear Register 1 .equ xlli_PLATFORM_PCMCIA0_SC_offset,(0xE0) @ PCMCIA Socket 0 Status/Control Register .equ xlli_PLATFORM_PCMCIA1_SC_offset,(0xE4) @ PCMCIA Socket 1 Status/Control Register@@ Platform specific bits@ .equ xlli_SYS_RESET,(0x01) @ System reset bit@@ platform GPIO pin settings (Bulverde/Mainstone)@ .equ xlli_GPSR0_value,(0x00008004) @ Set registers .equ xlli_GPSR1_value,(0x00020080) .equ xlli_GPSR2_value,(0x16C14000) .equ xlli_GPSR3_value,(0x0003E000) .equ xlli_GPCR0_value,(0x0) @ Clear registers .equ xlli_GPCR1_value,(0x00000380) @ FFUART related .equ xlli_GPCR2_value,(0x0) .equ xlli_GPCR3_value,(0x0) .equ xlli_GRER0_value,(0x0) @ Rising Edge Detect .equ xlli_GRER1_value,(0x0) .equ xlli_GRER2_value,(0x0) .equ xlli_GRER3_value,(0x0) .equ xlli_GFER0_value,(0x0) @ Falling Edge Detect .equ xlli_GFER1_value,(0x0) .equ xlli_GFER2_value,(0x0) .equ xlli_GFER3_value,(0x0) .equ xlli_GPLR0_value,(0x0) @ Pin Level Registers .equ xlli_GPLR1_value,(0x0) .equ xlli_GPLR2_value,(0x0) .equ xlli_GPLR3_value,(0x0) .equ xlli_GEDR0_value,(0x0) @ Edge Detect Status .equ xlli_GEDR1_value,(0x0) .equ xlli_GEDR2_value,(0x0) .equ xlli_GEDR3_value,(0x0) .equ xlli_GPDR0_value,(0xCFE3BDE4) @ Direction Registers .equ xlli_GPDR1_value,(0x003FAB81) .equ xlli_GPDR2_value,(0x1EC3FC00) .equ xlli_GPDR3_value,(0x018FFE8F) .equ xlli_GAFR0_L_value,(0x84400000) @ Alternate function registers .equ xlli_GAFR0_U_value,(0xA5000510) .equ xlli_GAFR1_L_value,(0x000A9558) .equ xlli_GAFR1_U_value,(0x0005A1AA) .equ xlli_GAFR2_L_value,(0x60000000) .equ xlli_GAFR2_U_value,(0x00000802) .equ xlli_GAFR3_L_value,(0x00000000) .equ xlli_GAFR3_U_value,(0x00000000)@@ MEMORY CONTROLLER SETTINGS FOR MAINSTONE@ .equ xlli_MDREFR_value,(0x0000001E) .ifdef xlli_MCP .equ xlli_MSC0_DC_value,(0x7FF0B8FA) @ Bulverde Card Flash value (MCP version) .else .equ xlli_MSC0_DC_value,(0x7FF0B8F2) @ Bulverde Card Flash value (Non-MCP version) .endif .equ xlli_MSC0_MS_value,(0x23F2B8F2) @ Mainstone Board Flash value .equ xlli_MSC1_value,(0x0000CCD1) .equ xlli_MSC2_value,(0x0000B884) .equ xlli_MECR_value,(0x00000001) .equ xlli_MCMEM0_value,(0x0001C391) .equ xlli_MCMEM1_value,(0x0001C391) .equ xlli_MCATT0_value,(0x0001C391) .equ xlli_MCATT1_value,(0x0001C391) .equ xlli_MCIO0_value,(0x0001C391) .equ xlli_MCIO1_value,(0x0001C391) .equ xlli_FLYCNFG_value,(0x00010001) .equ xlli_MDMRSLP_value,(0x0000C008) .equ xlli_SXCNFG_value,(0x40044004) @ Default value at boot up@@ Optimal values for MSCO for various MemClk frequencies are listed below@ These values are for K3 async flash@ .equ xlli_MSC0_13,(0x11101110) .equ xlli_MSC0_19,(0x11101110) .equ xlli_MSC0_26,(0x11201120) @ 26 MHz setting .equ xlli_MSC0_32,(0x11201120) .equ xlli_MSC0_39,(0x11301130) @ 39 MHz setting .equ xlli_MSC0_45,(0x11301130) .equ xlli_MSC0_52,(0x11401140) @ 52 MHz setting .equ xlli_MSC0_58,(0x11401140) .equ xlli_MSC0_65,(0x11501150) @ 65 MHz setting .equ xlli_MSC0_68,(0x11501150) .equ xlli_MSC0_71,(0x11501150) @ 71.5 MHz setting .equ xlli_MSC0_74,(0x11601160) .equ xlli_MSC0_78,(0x12601260) @ 78 MHz setting .equ xlli_MSC0_81,(0x12601260) .equ xlli_MSC0_84,(0x12601260) @ 84.5 MHz setting .equ xlli_MSC0_87,(0x12701270) .equ xlli_MSC0_91,(0x12701270) @ 91 MHz setting .equ xlli_MSC0_94,(0x12701270) @ 94.2 MHz setting .equ xlli_MSC0_97,(0x12701270) @ 97.5 MHz setting .equ xlli_MSC0_100,(0x12801280) @ 100.7 MHz setting .equ xlli_MSC0_104,(0x12801280) @ 104 MHz setting .equ xlli_MSC0_110,(0x12901290) .equ xlli_MSC0_117,(0x13901390) @ 117 MHz setting .equ xlli_MSC0_124,(0x13A013A0) .equ xlli_MSC0_130,(0x13A013A0) @ 130 MHz setting .equ xlli_MSC0_136,(0x13B013B0) .equ xlli_MSC0_143,(0x13B013B0) .equ xlli_MSC0_149,(0x13C013C0) .equ xlli_MSC0_156,(0x14C014C0) .equ xlli_MSC0_162,(0x14C014C0) .equ xlli_MSC0_169,(0x14C014C0) .equ xlli_MSC0_175,(0x14C014C0) .equ xlli_MSC0_182,(0x14C014C0) .equ xlli_MSC0_188,(0x14C014C0) .equ xlli_MSC0_195,(0x15C015C0) .equ xlli_MSC0_201,(0x15D015D0) .equ xlli_MSC0_208,(0x15D015D0)@@ Optimal values for DTC settings for various MemClk settings (MDCNFG)@ .equ xlli_DTC_13,(0x00000000) @ 13 MHz setting .equ xlli_DTC_19,(0x00000000) @ 19 MHz setting .equ xlli_DTC_26,(0x00000000) @ 26 MHz setting .equ xlli_DTC_32,(0x00000000) @ 32 MHz setting .equ xlli_DTC_39,(0x00000000) @ 39 MHz setting .equ xlli_DTC_45,(0x00000000) @ 45 MHz setting .equ xlli_DTC_52,(0x00000000) @ 52 MHz setting .equ xlli_DTC_58,(0x01000100) @ 58 MHz setting .equ xlli_DTC_65,(0x01000100) @ 65 MHz setting .equ xlli_DTC_68,(0x01000100) @ 68 MHz setting .equ xlli_DTC_71,(0x01000100) @ 71 MHz setting .equ xlli_DTC_74,(0x01000100) @ 74 MHz setting .equ xlli_DTC_78,(0x01000100) @ 78 MHz setting .equ xlli_DTC_81,(0x01000100) @ 81 MHz setting .equ xlli_DTC_84,(0x01000100) @ 84 MHz setting .equ xlli_DTC_87,(0x01000100) @ 87 MHz setting .equ xlli_DTC_91,(0x01000100) @ 91 MHz setting .equ xlli_DTC_94,(0x01000100) @ 94 MHz setting .equ xlli_DTC_97,(0x01000100) @ 97 MHz setting .equ xlli_DTC_100,(0x01000100) @ 100 MHz setting .equ xlli_DTC_104,(0x01000100) @ 104 MHz setting .equ xlli_DTC_110,(0x01000100) @ 110 MHz setting - SDCLK Halved .equ xlli_DTC_117,(0x01000100) @ 117 MHz setting - SDCLK Halved .equ xlli_DTC_124,(0x01000100) @ 124 MHz setting - SDCLK Halved .equ xlli_DTC_130,(0x01000100) @ 130 MHz setting - SDCLK Halved .equ xlli_DTC_136,(0x01000100) @ 136 MHz setting - SDCLK Halved .equ xlli_DTC_143,(0x01000100) @ 143 MHz setting - SDCLK Halved .equ xlli_DTC_149,(0x01000100) @ 149 MHz setting - SDCLK Halved .equ xlli_DTC_156,(0x01000100) @ 156 MHz setting - SDCLK Halved .equ xlli_DTC_162,(0x01000100) @ 162 MHz setting - SDCLK Halved .equ xlli_DTC_169,(0x01000100) @ 169 MHz setting - SDCLK Halved .equ xlli_DTC_175,(0x01000100) @ 175 MHz setting - SDCLK Halved .equ xlli_DTC_182,(0x01000100) @ 182 MHz setting - SDCLK Halved .equ xlli_DTC_188,(0x01000100) @ 188 MHz setting - SDCLK Halved .equ xlli_DTC_195,(0x01000100) @ 195 MHz setting - SDCLK Halved .equ xlli_DTC_201,(0x01000100) @ 201 MHz setting - SDCLK Halved .equ xlli_DTC_208,(0x01000100) @ 208 MHz setting - SDCLK Halved@@ Optimal values for DRI settings for various MemClk settings (MDREFR)@ .equ xlli_DRI_13,(0x002) @ 13 MHz setting .equ xlli_DRI_19,(0x003) .equ xlli_DRI_26,(0x005) @ 26 MHz setting .equ xlli_DRI_32,(0x006) .equ xlli_DRI_39,(0x008) @ 39 MHz setting .equ xlli_DRI_45,(0x00A) .equ xlli_DRI_52,(0x00B) @ 52 MHz setting .equ xlli_DRI_58,(0x00D) .equ xlli_DRI_65,(0x00E) @ 65 MHz setting .equ xlli_DRI_68,(0x00F) .equ xlli_DRI_71,(0x010) @ 71 MHz setting .equ xlli_DRI_74,(0x011) .equ xlli_DRI_78,(0x012) @ 78 MHz setting .equ xlli_DRI_81,(0x012) .equ xlli_DRI_84,(0x013) @ 84 MHz setting .equ xlli_DRI_87,(0x014) .equ xlli_DRI_91,(0x015) @ 91 MHz setting .equ xlli_DRI_94,(0x016) @ 94 MHz setting .equ xlli_DRI_97,(0x016) @ 97 MHz setting .equ xlli_DRI_100,(0x017) @ 100 MHz setting .equ xlli_DRI_104,(0x018) @ 104 MHz setting .equ xlli_DRI_110,(0x01A) .equ xlli_DRI_117,(0x01B) @ 117 MHz setting .equ xlli_DRI_124,(0x01D) .equ xlli_DRI_130,(0x01E) @ 130 MHz setting .equ xlli_DRI_136,(0x020) .equ xlli_DRI_143,(0x021) .equ xlli_DRI_149,(0x023) .equ xlli_DRI_156,(0x025) .equ xlli_DRI_162,(0x026) .equ xlli_DRI_169,(0x028) @ 169 MHz setting .equ xlli_DRI_175,(0x029) .equ xlli_DRI_182,(0x02B) .equ xlli_DRI_188,(0x02D) .equ xlli_DRI_195,(0x02E) .equ xlli_DRI_201,(0x030) .equ xlli_DRI_208,(0x031) @ 208 MHz setting@ SDRAM Settings .ifdef xlli_MCP .equ xlli_MDCNFG_value,(0x00002BCC) @ SDRAM Config Reg (MCP Version) .equ xlli_SDRAM_16BIT,0 @ Define so SDRAM init is for 16 bit bus .else .equ xlli_MDCNFG_value,(0x00000AC8) @ SDRAM Config Reg (Non-MCP Version) .endif .equ xlli_MDMRS_value,(0x00000000) @ SDRAM Mode Reg Set Config Reg@@ MEMORY PHYSICAL BASE ADDRESS(S)@ .equ xlli_SRAM_PHYSICAL_BASE,(0X5C000000) @ Physical base address for SRAM .equ xlli_SDRAM_PHYSICAL_BASE,(0xA0000000) @ Physical base address for SDRAM@@ CORE, SYSTEM BUS, MEMORY BUS Default frequency setting for Mainstone@ .equ xlli_CCCR_value,(0x00000107) @ Bulverde (HW reset value to start)@@ Clock Enable Register (CKEN) setting@ .equ xlli_CKEN_value,(0x00400200) @ Data to be set into the clock enable register @ bit 9 enables OS timers @ Bit 22 enables memory clock@@ Address where system configuration data is stored@ .equ xlli_SCR_data,(0x5C03FFFC) @ Address in SRAM where system config data is stored@@ Misc constants@ .equ xlli_MemSize_1Mb,(0x00100000) .ifdef xlli_MCP .equ xlli_p_PageTable,(0xA1FFC000) @ Base address for memory Page Table (MCP version) .else .equ xlli_p_PageTable,(0xA3FFC000) @ Base address for memory Page Table (Non-MCP version) .endif .equ xlli_s_PageTable,(0x00004000) @ Page Table size (4K words - 16 Kb) .ifdef POST_BUILD .equ xlli_v_xbBOOTROM,(0x04000000) @ (0x04000000 for POST) .else .equ xlli_v_xbBOOTROM,(0x00000000) .endif@ ⌨️ 快捷键说明
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