📄 sa1111.h
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/* * sa1111.h: Defines and macros for accessing the SA1111. Created from * the kernel source. * * Copyright (C) 2001 Stefan Eletzhofer <stefan.eletzhofer@www.eletztrick.de> * * $Id: sa1111.h,v 1.1 2003/08/06 23:00:52 abz Exp $ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * */#ident "$Id: sa1111.h,v 1.1 2003/08/06 23:00:52 abz Exp $"#ifndef BLOB_SA1111_H#define BLOB_SA1111_H#include <blob/arch.h>#include <blob/bitfield.h>#define SA1111_VBASE 0x40000000/* * 26 bits of the SA-1110 address bus are available to the SA-1111. * Use these when feeding target addresses to the DMA engines. */#define MEM_REG(adr) (*((u32 *)(adr)))#define SA1111_ADDR_WIDTH (26)#define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1)#define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK)/* * Don't ask the (SAC) DMA engines to move less than this amount. */#define SA1111_SAC_DMA_MIN_XFER (0x800)/* * SA1111 register definitions. */#define SA1111_REG(x) MEM_REG(SA1111_VBASE + (x))/* System Bus Interface (SBI) * * Registers * SKCR Control Register * SMCR Shared Memory Controller Register * SKID ID Register */#define SA1111_SKCR 0x0000#define SA1111_SMCR 0x0004#define SA1111_SKID 0x0008#define SBI_SKCR SA1111_REG(SA1111_SKCR)#define SBI_SMCR SA1111_REG(SA1111_SMCR)#define SBI_SKID SA1111_REG(SA1111_SKID)#define SKCR_PLL_BYPASS (1<<0)#define SKCR_RCLKEN (1<<1)#define SKCR_SLEEP (1<<2)#define SKCR_DOZE (1<<3)#define SKCR_VCO_OFF (1<<4)#define SKCR_SCANTSTEN (1<<5)#define SKCR_CLKTSTEN (1<<6)#define SKCR_RDYEN (1<<7)#define SKCR_SELAC (1<<8)#define SKCR_OPPC (1<<9)#define SKCR_PLLTSTEN (1<<10)#define SKCR_USBIOTSTEN (1<<11)/* * Don't believe the specs! Take them, throw them outside. Leave them * there for a week. Spit on them. Walk on them. Stamp on them. * Pour gasoline over them and finally burn them. Now think about coding. * - The October 1999 errata (278260-007) says its bit 13, 1 to enable. * - The Feb 2001 errata (278260-010) says that the previous errata * (278260-009) is wrong, and its bit actually 12, fixed in spec * 278242-003. * - The SA1111 manual (278242) says bit 12, but 0 to enable. * - Reality is bit 13, 1 to enable. * -- rmk */#define SKCR_OE_EN (1<<13)#define SMCR_DTIM (1<<0)#define SMCR_MBGE (1<<1)#define SMCR_DRAC_0 (1<<2)#define SMCR_DRAC_1 (1<<3)#define SMCR_DRAC_2 (1<<4)#define SMCR_DRAC Fld(3, 2)#define SMCR_CLAT (1<<5)#define SKID_SIREV_MASK (0x000000f0)#define SKID_MTREV_MASK (0x0000000f)#define SKID_ID_MASK (0xffffff00)#define SKID_SA1111_ID (0x690cc200)/* * System Controller * * Registers * SKPCR Power Control Register * SKCDR Clock Divider Register * SKAUD Audio Clock Divider Register * SKPMC PS/2 Mouse Clock Divider Register * SKPTC PS/2 Track Pad Clock Divider Register * SKPEN0 PWM0 Enable Register * SKPWM0 PWM0 Clock Register * SKPEN1 PWM1 Enable Register * SKPWM1 PWM1 Clock Register */#define SKPCR SA1111_REG(0x0200)#define SKCDR SA1111_REG(0x0204)#define SKAUD SA1111_REG(0x0208)#define SKPMC SA1111_REG(0x020c)#define SKPTC SA1111_REG(0x0210)#define SKPEN0 SA1111_REG(0x0214)#define SKPWM0 SA1111_REG(0x0218)#define SKPEN1 SA1111_REG(0x021c)#define SKPWM1 SA1111_REG(0x0220)#define SKPCR_UCLKEN (1<<0)#define SKPCR_ACCLKEN (1<<1)#define SKPCR_I2SCLKEN (1<<2)#define SKPCR_L3CLKEN (1<<3)#define SKPCR_SCLKEN (1<<4)#define SKPCR_PMCLKEN (1<<5)#define SKPCR_PTCLKEN (1<<6)#define SKPCR_DCLKEN (1<<7)#define SKPCR_PWMCLKEN (1<<8)/* * USB Host controller */#define USB_OHCI_OP_BASE SA1111_REG(0x0400)#define USB_STATUS SA1111_REG(0x0518)#define USB_RESET SA1111_REG(0x051c)#define USB_INTERRUPTEST SA1111_REG(0x0520)#define USB_RESET_FORCEIFRESET (1 << 0)#define USB_RESET_FORCEHCRESET (1 << 1)#define USB_RESET_CLKGENRESET (1 << 2)#define USB_RESET_SIMSCALEDOWN (1 << 3)#define USB_RESET_USBINTTEST (1 << 4)#define USB_RESET_SLEEPSTBYEN (1 << 5)#define USB_RESET_PWRSENSELOW (1 << 6)#define USB_RESET_PWRCTRLLOW (1 << 7)/* * Serial Audio Controller * * Registers * SACR0 Serial Audio Common Control Register * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register * SACR2 Serial Audio AC-link Control Register * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register * SASR1 Serial Audio AC-link Interface & FIFO Status Register * SASCR Serial Audio Status Clear Register * L3_CAR L3 Control Bus Address Register * L3_CDR L3 Control Bus Data Register * ACCAR AC-link Command Address Register * ACCDR AC-link Command Data Register * ACSAR AC-link Status Address Register * ACSDR AC-link Status Data Register * SADTCS Serial Audio DMA Transmit Control/Status Register * SADTSA Serial Audio DMA Transmit Buffer Start Address A * SADTCA Serial Audio DMA Transmit Buffer Count Register A * SADTSB Serial Audio DMA Transmit Buffer Start Address B * SADTCB Serial Audio DMA Transmit Buffer Count Register B * SADRCS Serial Audio DMA Receive Control/Status Register * SADRSA Serial Audio DMA Receive Buffer Start Address A * SADRCA Serial Audio DMA Receive Buffer Count Register A * SADRSB Serial Audio DMA Receive Buffer Start Address B * SADRCB Serial Audio DMA Receive Buffer Count Register B * SAITR Serial Audio Interrupt Test Register * SADR Serial Audio Data Register (16 x 32-bit) */#define SACR0 SA1111_REG(0x0600)#define SACR1 SA1111_REG(0x0604)#define SACR2 SA1111_REG(0x0608)#define SASR0 SA1111_REG(0x060c)#define SASR1 SA1111_REG(0x0610)#define SASCR SA1111_REG(0x0618)#define L3_CAR SA1111_REG(0x061c)#define L3_CDR SA1111_REG(0x0620)#define ACCAR SA1111_REG(0x0624)#define ACCDR SA1111_REG(0x0628)#define ACSAR SA1111_REG(0x062c)#define ACSDR SA1111_REG(0x0630)#define SADTCS SA1111_REG(0x0634)#define SADTSA SA1111_REG(0x0638)#define SADTCA SA1111_REG(0x063c)#define SADTSB SA1111_REG(0x0640)#define SADTCB SA1111_REG(0x0644)#define SADRCS SA1111_REG(0x0648)#define SADRSA SA1111_REG(0x064c)#define SADRCA SA1111_REG(0x0650)#define SADRSB SA1111_REG(0x0654)#define SADRCB SA1111_REG(0x0658)#define SAITR SA1111_REG(0x065c)#define SADR SA1111_REG(0x0680)#define SACR0_ENB (1<<0)#define SACR0_BCKD (1<<2)#define SACR0_RST (1<<3)#define SACR1_AMSL (1<<0)#define SACR1_L3EN (1<<1)#define SACR1_L3MB (1<<2)#define SACR1_DREC (1<<3)#define SACR1_DRPL (1<<4)#define SACR1_ENLBF (1<<5)#define SACR2_TS3V (1<<0)#define SACR2_TS4V (1<<1)#define SACR2_WKUP (1<<2)#define SACR2_DREC (1<<3)#define SACR2_DRPL (1<<4)#define SACR2_ENLBF (1<<5)#define SACR2_RESET (1<<6)#define SASR0_TNF (1<<0)#define SASR0_RNE (1<<1)#define SASR0_BSY (1<<2)#define SASR0_TFS (1<<3)#define SASR0_RFS (1<<4)#define SASR0_TUR (1<<5)#define SASR0_ROR (1<<6)#define SASR0_L3WD (1<<16)#define SASR0_L3RD (1<<17)#define SASR1_TNF (1<<0)#define SASR1_RNE (1<<1)#define SASR1_BSY (1<<2)#define SASR1_TFS (1<<3)#define SASR1_RFS (1<<4)#define SASR1_TUR (1<<5)#define SASR1_ROR (1<<6)#define SASR1_CADT (1<<16)#define SASR1_SADR (1<<17)#define SASR1_RSTO (1<<18)#define SASR1_CLPM (1<<19)#define SASR1_CRDY (1<<20)#define SASR1_RS3V (1<<21)#define SASR1_RS4V (1<<22)#define SASCR_TUR (1<<5)#define SASCR_ROR (1<<6)#define SASCR_DTS (1<<16)#define SASCR_RDD (1<<17)#define SASCR_STO (1<<18)#define SADTCS_TDEN (1<<0)#define SADTCS_TDIE (1<<1)#define SADTCS_TDBDA (1<<3)#define SADTCS_TDSTA (1<<4)#define SADTCS_TDBDB (1<<5)#define SADTCS_TDSTB (1<<6)#define SADTCS_TBIU (1<<7)#define SADRCS_RDEN (1<<0)#define SADRCS_RDIE (1<<1)#define SADRCS_RDBDA (1<<3)#define SADRCS_RDSTA (1<<4)⌨️ 快捷键说明
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