system3.h

pxa270的bootloader,linux下的,好不容易搞到的

/*
 * system3.h: PT system3 specific defines
 *
 * Copyright (C) 2001  Erik Mouw ([e-mail])
 *
 * $Id: system3.h,v 1.20 2003/08/21 12:43:44 seletz Exp $
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#ident "$Id: system3.h,v 1.20 2003/08/21 12:43:44 seletz Exp $"

#ifndef BLOB_ARCH_SYSTEM3_H
#define BLOB_ARCH_SYSTEM3_H

//#define	CPU_SPEED_133
#undef	CPU_SPEED_133

/* SYSTEM3 with 64 MB SDRAM, all on bank0 */
//#undef CONFIG_SYSTEM3_REV0802
#define CONFIG_SYSTEM3_REV0802

/* boot CPU speed */
#ifdef CPU_SPEED_133
#	define CPU_SPEED		(CPU_CORE_SPEED_132mhz)
#else
#	define CPU_SPEED		(CPU_CORE_SPEED_206mhz)
#endif

/* serial port */
#define USE_SERIAL1
#define TERMINAL_SPEED baud_115200

/* GPIO for the LED */
//#define LED_GPIO		(0x00800000) /* GPIO 10 */
#define LED_GPIO		(0x00000000) /* NO LED */


/* the base address were BLOB is loaded by the first stage loader */
#define BLOB_ABS_BASE_ADDR	(0xc0200400)


/* where do various parts live in RAM */
#define BLOB_RAM_BASE		(0xc0100000)
#define KERNEL_RAM_BASE		(0xC0008000)
#define PARAM_RAM_BASE		(0xc0110000)
#define RAMDISK_RAM_BASE	(0xC0400000)

/* hmm, do i need these ? */
#define PARAM_FLASH_BASE	(0x00040000)
#define PARAM_FLASH_LEN		(256 * 1024)


/* and where do they live in flash */
#define BLOB_FLASH_BASE		(0x00000000)
#define BLOB_FLASH_LEN		(0x00040000)
#define CONFIG_FLASH_BASE	(BLOB_FLASH_BASE + BLOB_FLASH_LEN)
#define CONFIG_FLASH_LEN	(0x00040000)
#define KERNEL_FLASH_BASE	(CONFIG_FLASH_BASE + CONFIG_FLASH_LEN)
#define KERNEL_FLASH_LEN	(0x00100000)
#define RAMDISK_FLASH_BASE	(KERNEL_FLASH_BASE + KERNEL_FLASH_LEN)
#define RAMDISK_FLASH_LEN	(0x00180000)
#define ROOTFS_FLASH_BASE	(RAMDISK_FLASH_BASE + RAMDISK_FLASH_LEN)
#define ROOTFS_FLASH_LEN	(0x00700000)
#define DATAFS_FLASH_BASE	(ROOTFS_FLASH_BASE + ROOTFS_FLASH_LEN)
#define DATAFS_FLASH_LEN	(0x015c0000)
#define XDATAFS_FLASH_BASE	(DATAFS_FLASH_BASE + DATAFS_FLASH_LEN)
#define XDATAFS_FLASH_LEN	(0x00040000)
#define LOAD_RAMDISK		1 /* load ramdisk into ram */

/* system3 RAM pool for up/downloading */
#if !defined(CONFIG_SYSTEM3_REV0802)
#define RAM_START			(0xd0000000)
#define RAM_SIZE			(16*1024*1024)
#else
#define RAM_START			(0xc1000000)
#define RAM_SIZE			(0x03000000)
#endif


/* the position of the kernel boot parameters */
#define BOOT_PARAMS		(0xc0000100)


/* the size (in kbytes) to which the compressed ramdisk expands */
#define RAMDISK_SIZE		(8 * 1024)

/* let SDRAM run at FULL memclk speed */
#define MDREFR_MEMCLK_FULLSPEED_0
#define MDREFR_MEMCLK_FULLSPEED_1
#define MDREFR_MEMCLK_FULLSPEED_2

/* Memory configuration */
#ifdef BLOB_NEED_MEMCONFIG
#define MSC0_VALUE_66_150	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(10) | MSC_RDN(2) | MSC_RRR(1)
#define MSC0_VALUE_66_120	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF( 8) | MSC_RDN(2) | MSC_RRR(1)
#define MSC0_VALUE_66_100	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF( 7) | MSC_RDN(2) | MSC_RRR(1)
#define MSC1_VALUE_66		MSC_RT_ROMFLASH | MSC_RBW16 | MSC_RDF(5)  | MSC_RDN(1) | MSC_RRR(1) | ((MSC_RT_VARLAT_345 | MSC_RBW16 | MSC_RDF(30)  | MSC_RDN(30) | MSC_RRR(7))<<16)
#define MSC2_VALUE_66		MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(13)  | MSC_RDN(6) | MSC_RRR(3)
#define MECR_VALUE_66		MECR_BSIO0(0x1f) | MECR_BSA0(0x1f) | MECR_BSM0(0x1f) | MECR_BSIO1(0x1f) | MECR_BSA1(0x1f) | MECR_BSM1(0x1f)

#define MSC0_VALUE_100_150	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(16) | MSC_RDN(3) | MSC_RRR(2)
#define MSC0_VALUE_100_120	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(13) | MSC_RDN(3) | MSC_RRR(2)
#define MSC0_VALUE_100_100	MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(11) | MSC_RDN(3) | MSC_RRR(2)
#define MSC1_VALUE_100		MSC_RT_ROMFLASH | MSC_RBW16 | MSC_RDF(5)  | MSC_RDN(1) | MSC_RRR(1)| ((MSC_RT_VARLAT_345 | MSC_RBW16 | MSC_RDF(30)  | MSC_RDN(30) | MSC_RRR(7))<<16)
#define MSC2_VALUE_100		MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(13)  | MSC_RDN(6) | MSC_RRR(3)
#define MECR_VALUE_100		MECR_BSIO0(0x1f) | MECR_BSA0(0x1f) | MECR_BSM0(0x1f) | MECR_BSIO1(0x1f) | MECR_BSA1(0x1f) | MECR_BSM1(0x1f)

#ifndef CPU_SPEED_133
//	206 Mhz
#if defined(CONFIG_SYSTEM3_REV0802)
#	define MDCNFG_VALUE	MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(6) | MDCNFG_CDB20(0) | MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(1) | \
						MDCNFG_DTIM2_SDRAM | MDCNFG_DWID2_32B | MDCNFG_DRAC2(6) | MDCNFG_CDB22(0) | MDCNFG_TRP2(2) | MDCNFG_TDL2(3) | MDCNFG_TWR2(1)
#else
#	define MDCNFG_VALUE	MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(5) | MDCNFG_CDB20(0) | MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(1) | \
						MDCNFG_DTIM2_SDRAM | MDCNFG_DWID2_32B | MDCNFG_DRAC2(5) | MDCNFG_CDB22(0) | MDCNFG_TRP2(2) | MDCNFG_TDL2(3) | MDCNFG_TWR2(1)
#endif
#	define MDCAS00_VALUE	0xAAAAAA9F
#	define MDCAS01_VALUE	0xAAAAAAAA
#	define MDCAS02_VALUE	0xAAAAAAAA
#	define MDCAS20_VALUE	0xAAAAAA9F
#	define MDCAS21_VALUE	0xAAAAAAAA
#	define MDCAS22_VALUE	0xAAAAAAAA
#	define MSC0_VALUE	MSC0_VALUE_100_150
#	define MSC1_VALUE	MSC1_VALUE_100
#	define MSC2_VALUE	MSC2_VALUE_100
#	define MECR_VALUE	MECR_VALUE_100
#	define SMCNFG_VALUE	0
#else
//	133 Mhz
#if defined(CONFIG_SYSTEM3_REV0802)
#	define MDCNFG_VALUE	MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(6) | MDCNFG_CDB20(0) | MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(1) | \
						MDCNFG_DTIM2_SDRAM | MDCNFG_DWID2_32B | MDCNFG_DRAC2(6) | MDCNFG_CDB22(0) | MDCNFG_TRP2(2) | MDCNFG_TDL2(3) | MDCNFG_TWR2(1)
#else
#	define MDCNFG_VALUE	MDCNFG_DTIM0_SDRAM | MDCNFG_DWID0_32B | MDCNFG_DRAC0(5) | MDCNFG_CDB20(0) | MDCNFG_TRP0(2) | MDCNFG_TDL0(3) | MDCNFG_TWR0(1) | \
						MDCNFG_DTIM2_SDRAM | MDCNFG_DWID2_32B | MDCNFG_DRAC2(5) | MDCNFG_CDB22(0) | MDCNFG_TRP2(2) | MDCNFG_TDL2(3) | MDCNFG_TWR2(1)
#endif
#	define MDCAS00_VALUE	0xAAAAAA9F
#	define MDCAS01_VALUE	0xAAAAAAAA
#	define MDCAS02_VALUE	0xAAAAAAAA
#	define MDCAS20_VALUE	0xAAAAAA9F
#	define MDCAS21_VALUE	0xAAAAAAAA
#	define MDCAS22_VALUE	0xAAAAAAAA
#	define MSC0_VALUE	MSC0_VALUE_66_150
#	define MSC1_VALUE	MSC1_VALUE_66
#	define MSC2_VALUE	MSC2_VALUE_66
#	define MECR_VALUE	MECR_VALUE_66
#	define SMCNFG_VALUE	0
#endif
#endif

/* Debugging macros used in system 3 code */
#define SYSTEM3_DEBUG 1

#ifdef SYSTEM3_DEBUG
#	define _DBGU32( x )	SerialOutputString( #x"=0x" ); \
				SerialOutputHex( (u32)x ); \
				serial_write( '\n' );
#else
#	define _DBGU32( x )
#endif

#define	SA1111_BASE		(0x40000000)

#define SYSTEM3_SYSID		(0x10000000)
#define SYSTEM3_CTRL_0		(0x10000090)
#define SYSTEM3_CTRL_1		(0x100000A0)
#define SYSTEM3_CTRL_2		(0x100000B0)
#define SYSTEM3_CTRL_IRR	(0x10000024)

/* System ID register */
#define PT_SYSID	(*((volatile u8 *)SYSTEM3_SYSID))
#define PT_ID_BOARDID	(( PT_SYSID & 0xE0 ) >> 5 )
#define PT_ID_REVISION	( PT_SYSID & 0x1F )

#define PT_BOARD_ALPHA	( 0 )
#define PT_BOARD_SYS3	( 1 )
#define PT_BOARD_DAFIT	( 2 )

#endif