badge4.h

pxa270的bootloader,linux下的,好不容易搞到的

/*
 * badge4.h: BadgePAD 4 specific defines
 *
 * Copyright (C) 2001-2002  Hewlett-Packard Company
 * Written by Christopher Hoover <[e-mail]>
 *
 * $Id: badge4.h,v 1.15 2003/01/28 03:44:41 choover Exp $
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#ident "$Id: badge4.h,v 1.15 2003/01/28 03:44:41 choover Exp $"

#ifndef BLOB_ARCH_BADGE4_H
#define BLOB_ARCH_BADGE4_H

#define BADGE4_SA1111_BASE		(0x48000000)

/* GPIOs on the BadgePAD 4 */
#define BADGE4_GPIO_INT_1111		GPIO_GPIO0   /* SA-1111 IRQ */

#define BADGE4_GPIO_INT_VID		GPIO_GPIO1   /* Video expansion */
#define BADGE4_GPIO_LGP2		GPIO_GPIO2   /* GPIO_LDD8 */
#define BADGE4_GPIO_LGP3		GPIO_GPIO3   /* GPIO_LDD9 */
#define BADGE4_GPIO_LGP4		GPIO_GPIO4   /* GPIO_LDD10 */
#define BADGE4_GPIO_LGP5		GPIO_GPIO5   /* GPIO_LDD11 */
#define BADGE4_GPIO_LGP6		GPIO_GPIO6   /* GPIO_LDD12 */
#define BADGE4_GPIO_LGP7		GPIO_GPIO7   /* GPIO_LDD13 */
#define BADGE4_GPIO_LGP8		GPIO_GPIO8   /* GPIO_LDD14 */
#define BADGE4_GPIO_LGP9		GPIO_GPIO9   /* GPIO_LDD15 */
#define BADGE4_GPIO_GPA_VID		GPIO_GPIO10  /* Video expansion */
#define BADGE4_GPIO_GPB_VID		GPIO_GPIO11  /* Video expansion */
#define BADGE4_GPIO_GPC_VID		GPIO_GPIO12  /* Video expansion */

#define BADGE4_GPIO_UART_HS1		GPIO_GPIO13
#define BADGE4_GPIO_UART_HS2		GPIO_GPIO14

#define BADGE4_GPIO_MUXSEL0		GPIO_GPIO15
#define BADGE4_GPIO_TESTPT_J7		GPIO_GPIO16

#define BADGE4_GPIO_SDSDA		GPIO_GPIO17  /* SDRAM SPD Data */
#define BADGE4_GPIO_SDSCL		GPIO_GPIO18  /* SDRAM SPD Clock */
#define BADGE4_GPIO_SDTYP0		GPIO_GPIO19  /* SDRAM Type Control */
#define BADGE4_GPIO_SDTYP1		GPIO_GPIO20  /* SDRAM Type Control */

#define BADGE4_GPIO_BGNT_1111		GPIO_GPIO21  /* GPIO_MBGNT */
#define BADGE4_GPIO_BREQ_1111		GPIO_GPIO22  /* GPIO_TREQA */

#define BADGE4_GPIO_TESTPT_J6		GPIO_GPIO23

#define BADGE4_GPIO_PCMEN5V		GPIO_GPIO24  /* 5V power */

#define BADGE4_GPIO_SA1111_NRST		GPIO_GPIO25  /* SA-1111 nRESET */

#define BADGE4_GPIO_TESTPT_J5		GPIO_GPIO26

#define BADGE4_GPIO_CLK_1111		GPIO_GPIO27  /* GPIO_32_768kHz */

/* Interrupts on the BadgePAD 4 */
#define BADGE4_IRQ_GPIO_SA1111		IRQ_GPIO0    /* SA-1111 interrupt */

/* boot CPU speed */
#define CPU_SPEED		CPU_CORE_SPEED_206mhz

/* serial port */
#define USE_SERIAL3
#define TERMINAL_SPEED baud_115200

/* GPIO for the LED */
#define LED_GPIO		(1<<9)  /* GPIO_GPIO9/BADGE4_GPIO_LGP9 */

#define SA1111_BASE		BADGE4_SA1111_BASE

/* the base address were BLOB is loaded by the first stage loader */
#define BLOB_ABS_BASE_ADDR	(0x08000400)  /* sram */

/* where do various parts live in RAM */
#define BLOB_RAM_BASE		(0xc0100000)
#define KERNEL_RAM_BASE		(0xc0008000)
#define PARAM_RAM_BASE		(0xc0110000)
#define RAMDISK_RAM_BASE	(0xc0600000)

/* and where do they live in flash */
#ifdef CONFIG_ZIMAGE_SUPPORT

#  define BLOB_FLASH_BASE	(0x00000000)
#  define BLOB_FLASH_LEN	(0x00002000 * 6)
#  define PARAM_FLASH_BASE	(BLOB_FLASH_BASE + BLOB_FLASH_LEN)
#  define PARAM_FLASH_LEN	(0x00002000 * 2)
#  define KERNEL_FLASH_BASE	(PARAM_FLASH_BASE + PARAM_FLASH_LEN)
#  define KERNEL_FLASH_LEN	(0x00010000 * 16)
#  define RAMDISK_FLASH_BASE	(KERNEL_FLASH_BASE + KERNEL_FLASH_LEN)
#  define RAMDISK_FLASH_LEN	(0x00010000 * (127 - 16)) /* limit for d/l only */

#else

#  define BLOB_FLASH_BASE	(0x00000000)
#  define BLOB_FLASH_LEN	(0x00002000 * 6)
#  define PARAM_FLASH_BASE	(BLOB_FLASH_BASE + BLOB_FLASH_LEN)
#  define PARAM_FLASH_LEN	(0x00002000 * 2)
#  define RAMDISK_FLASH_BASE	(PARAM_FLASH_BASE + PARAM_FLASH_LEN)
#  define RAMDISK_FLASH_LEN	(0x00010000 * (127 - 16)) /* limit for d/l only */

#  define KERNEL_FLASH_LEN	(2 * 1024 * 1024) /* limit for d/l only */

#endif

#define PARAM_START		PARAM_FLASH_BASE
#define PARAM_LEN		PARAM_FLASH_LEN

#define LOAD_RAMDISK		0
#define RAMDISK_SIZE		(4 * 1024)


/* the position of the kernel boot parameters */
#define BOOT_PARAMS		(0xc0000100)

/* Memory configuration */

#define BADGE4_MDCNFG \
  (MDCNFG_BANK0_ENABLE|MDCNFG_DTIM0_SDRAM|MDCNFG_DWID0_32B|\
   MDCNFG_DRAC0(3)|MDCNFG_TRP0(4)|MDCNFG_TDL0(3)|MDCNFG_TWR0(3))

/* On CS0: Intel TE28F320C3 or TE28F640C3 Flash */
#define BADGE4_CS0 \
   (MSC_RT_ROMFLASH|MSC_RBW16|MSC_RDF(31)|MSC_RDN(31)|MSC_RRR(7))

/* On CS1: 2 x Toshbia TC55V400 FT-85 (SRAM 256K x 16 bit) [1MB total] */
#define BADGE4_CS1 \
   (MSC_RT_SRAM_012|MSC_RBW32|MSC_RDF(31)|MSC_RDN(31)|MSC_RRR(7))

/* On CS2: 2 x Toshbia TC55V400 FT-85 (SRAM 256K x 16 bit) [1MB total] */
#define BADGE4_CS2 \
   (MSC_RT_SRAM_012|MSC_RBW32|MSC_RDF(31)|MSC_RDN(31)|MSC_RRR(7))

/* On CS3: Nothing */
#define BADGE4_CS3 0

/* On CS4: Nothing */
#define BADGE4_CS4 0

/* On CS5: SA-1111 */
#define BADGE4_CS5 \
   (MSC_RT_SRAM_012|MSC_RBW32|MSC_RDF(31)|MSC_RDN(31)|MSC_RRR(7))

#define BADGE4_MSC0 (BADGE4_CS0 | (BADGE4_CS1<<16))
#define BADGE4_MSC1 (BADGE4_CS2 | (BADGE4_CS3<<16))
#define BADGE4_MSC2 (BADGE4_CS4 | (BADGE4_CS5<<16))

#define MDCNFG_VALUE	BADGE4_MDCNFG		/* 0x0  MDCNFG */
#define MDCAS00_VALUE	0xAAAAAAA7		/* 0x04 MDCAS00 */
#define MDCAS01_VALUE	0xAAAAAAAA		/* 0x08 MDCAS01 */
#define MDCAS02_VALUE	0xAAAAAAAA		/* 0x0c MDCAS02 */
#define MSC0_VALUE	BADGE4_MSC0		/* 0x10 MSC0 */
#define MSC1_VALUE	BADGE4_MSC1		/* 0x14 MSC1 */
#define MECR_VALUE	0x994a994a		/* 0x18 MECR */
#define MDREFR_VALUE	DO_NOT_USE_THIS_VALUE__GETS_AUTOMAGICALLY_COMPUTED
#define MDCAS20_VALUE	0xAAAAAA7F		/* 0x20 MDCAS20 */
#define MDCAS21_VALUE	0xAAAAAAAA		/* 0x24 MDCAS21 */
#define MDCAS22_VALUE	0xAAAAAAAA		/* 0x28 MDCAS22 */
#define MSC2_VALUE	BADGE4_MSC2		/* 0x2C MSC2 */
#define SMCNFG_VALUE	0x00000000		/* 0x30 SMCNFG */

#endif