📄 pocprinter.rpt
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| | +--------------------------- LC18 pd2
| | | +------------------------- LC17 pd3
| | | | +----------------------- LC20 pd4
| | | | | +--------------------- LC23 |POC:2|:11
| | | | | | +------------------- LC30 |POC:2|br4
| | | | | | | +----------------- LC31 |POC:2|br3
| | | | | | | | +--------------- LC32 |POC:2|br2
| | | | | | | | | +------------- LC26 |POC:2|br1
| | | | | | | | | | +----------- LC28 |POC:2|br0
| | | | | | | | | | | +--------- LC22 |printer:1|~2~1
| | | | | | | | | | | | +------- LC25 |printer:1|74193:7|QD
| | | | | | | | | | | | | +----- LC24 |printer:1|74193:7|QC
| | | | | | | | | | | | | | +--- LC27 |printer:1|74193:7|QB
| | | | | | | | | | | | | | | +- LC29 |printer:1|74193:7|QA
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC21 -> * - - - - - - - - - - - - - - - | - * | <-- pd0
LC19 -> - * - - - - - - - - - - - - - - | - * | <-- pd1
LC18 -> - - * - - - - - - - - - - - - - | - * | <-- pd2
LC17 -> - - - * - - - - - - - - - - - - | - * | <-- pd3
LC20 -> - - - - * - - - - - - - - - - - | - * | <-- pd4
LC23 -> - - - - - * - - - - - * * * * * | - * | <-- |POC:2|:11
LC30 -> - - - - * - * - - - - - - - - - | - * | <-- |POC:2|br4
LC31 -> - - - * - - - * - - - - - - - - | - * | <-- |POC:2|br3
LC32 -> - - * - - - - - * - - - - - - - | - * | <-- |POC:2|br2
LC26 -> - * - - - - - - - * - - - - - - | - * | <-- |POC:2|br1
LC28 -> * - - - - - - - - - * - - - - - | - * | <-- |POC:2|br0
LC22 -> * * * * * * * * * * * * * * * * | * * | <-- |printer:1|~2~1
LC25 -> - - - - - - - - - - - * * - - - | - * | <-- |printer:1|74193:7|QD
LC24 -> - - - - - - - - - - - * * * - - | - * | <-- |printer:1|74193:7|QC
LC27 -> - - - - - - - - - - - * * * * - | - * | <-- |printer:1|74193:7|QB
LC29 -> - - - - - - - - - - - * * * * * | - * | <-- |printer:1|74193:7|QA
Pin
43 -> - - - - - - - - - - - * * * * * | - * | <-- clk
13 -> - - - - - - - - - - * - - - - - | - * | <-- D0
12 -> - - - - - - - - - * - - - - - - | - * | <-- D1
11 -> - - - - - - - - * - - - - - - - | - * | <-- D2
9 -> - - - - - - - * - - - - - - - - | - * | <-- D3
8 -> - - - - - - * - - - - - - - - - | - * | <-- D4
4 -> - - - - - - - - - - - * - - - - | - * | <-- reset
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\vhdl\pocprinter.rpt
pocprinter
** EQUATIONS **
clk : INPUT;
D0 : INPUT;
D1 : INPUT;
D2 : INPUT;
D3 : INPUT;
D4 : INPUT;
D5 : INPUT;
D6 : INPUT;
D7 : INPUT;
reset : INPUT;
-- Node name is 'pd0' = '|POC:2|:27'
-- Equation name is 'pd0', type is output
pd0 = DFFE( _EQ001 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC022 & _LC028
# !_LC022 & pd0;
-- Node name is 'pd1' = '|POC:2|:25'
-- Equation name is 'pd1', type is output
pd1 = DFFE( _EQ002 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC022 & _LC026
# !_LC022 & pd1;
-- Node name is 'pd2' = '|POC:2|:23'
-- Equation name is 'pd2', type is output
pd2 = DFFE( _EQ003 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC022 & _LC032
# !_LC022 & pd2;
-- Node name is 'pd3' = '|POC:2|:21'
-- Equation name is 'pd3', type is output
pd3 = DFFE( _EQ004 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC022 & _LC031
# !_LC022 & pd3;
-- Node name is 'pd4' = '|POC:2|:19'
-- Equation name is 'pd4', type is output
pd4 = DFFE( _EQ005 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = _LC022 & _LC030
# !_LC022 & pd4;
-- Node name is 'pd5' = '|POC:2|:17'
-- Equation name is 'pd5', type is output
pd5 = DFFE( _EQ006 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC004 & _LC022
# !_LC022 & pd5;
-- Node name is 'pd6' = '|POC:2|:15'
-- Equation name is 'pd6', type is output
pd6 = DFFE( _EQ007 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC005 & _LC022
# !_LC022 & pd6;
-- Node name is 'pd7' = '|POC:2|:13'
-- Equation name is 'pd7', type is output
pd7 = DFFE( _EQ008 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC006 & _LC022
# !_LC022 & pd7;
-- Node name is '|POC:2|:37' = '|POC:2|br0'
-- Equation name is '_LC028', type is buried
_LC028 = TFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = D0 & !_LC022 & !_LC028
# !D0 & !_LC022 & _LC028;
-- Node name is '|POC:2|:36' = '|POC:2|br1'
-- Equation name is '_LC026', type is buried
_LC026 = TFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = D1 & !_LC022 & !_LC026
# !D1 & !_LC022 & _LC026;
-- Node name is '|POC:2|:35' = '|POC:2|br2'
-- Equation name is '_LC032', type is buried
_LC032 = TFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = D2 & !_LC022 & !_LC032
# !D2 & !_LC022 & _LC032;
-- Node name is '|POC:2|:34' = '|POC:2|br3'
-- Equation name is '_LC031', type is buried
_LC031 = TFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = D3 & !_LC022 & !_LC031
# !D3 & !_LC022 & _LC031;
-- Node name is '|POC:2|:33' = '|POC:2|br4'
-- Equation name is '_LC030', type is buried
_LC030 = TFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = D4 & !_LC022 & !_LC030
# !D4 & !_LC022 & _LC030;
-- Node name is '|POC:2|:32' = '|POC:2|br5'
-- Equation name is '_LC004', type is buried
_LC004 = TFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = D5 & !_LC004 & !_LC022
# !D5 & _LC004 & !_LC022;
-- Node name is '|POC:2|:31' = '|POC:2|br6'
-- Equation name is '_LC005', type is buried
_LC005 = TFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = D6 & !_LC005 & !_LC022
# !D6 & _LC005 & !_LC022;
-- Node name is '|POC:2|:30' = '|POC:2|br7'
-- Equation name is '_LC006', type is buried
_LC006 = TFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = D7 & !_LC006 & !_LC022
# !D7 & _LC006 & !_LC022;
-- Node name is '|POC:2|:11'
-- Equation name is '_LC023', type is buried
_LC023 = TFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = _LC022 & !_LC023;
-- Node name is '|printer:1|~2~1'
-- Equation name is '_LC022', type is buried
-- synthesized logic cell
_LC022 = LCELL( _EQ018 $ !reset);
_EQ018 = clk & !_LC024 & !_LC025 & !_LC027 & !_LC029 & reset
# _LC022 & !_LC023 & reset;
-- Node name is '|printer:1|74193:7|:26' = '|printer:1|74193:7|QA'
-- Equation name is '_LC029', type is buried
_LC029 = TFFE( VCC, _EQ019, VCC, !_LC023, VCC);
_EQ019 = _X001 & _X002;
_X001 = EXP( clk & !_LC022);
_X002 = EXP( clk & _LC023);
-- Node name is '|printer:1|74193:7|:25' = '|printer:1|74193:7|QB'
-- Equation name is '_LC027', type is buried
_LC027 = TFFE( VCC, _EQ020, !_LC023, VCC, VCC);
_EQ020 = _X003 & _X004;
_X003 = EXP( clk & !_LC022 & !_LC029);
_X004 = EXP( clk & _LC023 & !_LC029);
-- Node name is '|printer:1|74193:7|:24' = '|printer:1|74193:7|QC'
-- Equation name is '_LC024', type is buried
_LC024 = TFFE( VCC, _EQ021, VCC, !_LC023, VCC);
_EQ021 = _X005 & _X006;
_X005 = EXP( clk & !_LC022 & !_LC027 & !_LC029);
_X006 = EXP( clk & _LC023 & !_LC027 & !_LC029);
-- Node name is '|printer:1|74193:7|:23' = '|printer:1|74193:7|QD'
-- Equation name is '_LC025', type is buried
_LC025 = TFFE( VCC, _EQ022, !_LC023, VCC, VCC);
_EQ022 = _X007 & _X008;
_X007 = EXP( clk & !_LC022 & !_LC024 & !_LC027 & !_LC029);
_X008 = EXP( clk & _LC023 & !_LC024 & !_LC027 & !_LC029);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\vhdl\pocprinter.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,076K
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