📄 poc.rpt
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+------------------------------- LC22 pd0
| +----------------------------- LC24 pd1
| | +--------------------------- LC23 pd2
| | | +------------------------- LC21 pd3
| | | | +----------------------- LC20 pd4
| | | | | +--------------------- LC19 pd5
| | | | | | +------------------- LC18 pd6
| | | | | | | +----------------- LC17 pd7
| | | | | | | | +--------------- LC31 br7
| | | | | | | | | +------------- LC30 br6
| | | | | | | | | | +----------- LC28 br5
| | | | | | | | | | | +--------- LC27 br4
| | | | | | | | | | | | +------- LC26 br3
| | | | | | | | | | | | | +----- LC29 br2
| | | | | | | | | | | | | | +--- LC25 br1
| | | | | | | | | | | | | | | +- LC32 br0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC22 -> * - - - - - - - - - - - - - - - | - * | <-- pd0
LC24 -> - * - - - - - - - - - - - - - - | - * | <-- pd1
LC23 -> - - * - - - - - - - - - - - - - | - * | <-- pd2
LC21 -> - - - * - - - - - - - - - - - - | - * | <-- pd3
LC20 -> - - - - * - - - - - - - - - - - | - * | <-- pd4
LC19 -> - - - - - * - - - - - - - - - - | - * | <-- pd5
LC18 -> - - - - - - * - - - - - - - - - | - * | <-- pd6
LC17 -> - - - - - - - * - - - - - - - - | - * | <-- pd7
LC31 -> - - - - - - - * * - - - - - - - | - * | <-- br7
LC30 -> - - - - - - * - - * - - - - - - | - * | <-- br6
LC28 -> - - - - - * - - - - * - - - - - | - * | <-- br5
LC27 -> - - - - * - - - - - - * - - - - | - * | <-- br4
LC26 -> - - - * - - - - - - - - * - - - | - * | <-- br3
LC29 -> - - * - - - - - - - - - - * - - | - * | <-- br2
LC25 -> - * - - - - - - - - - - - - * - | - * | <-- br1
LC32 -> * - - - - - - - - - - - - - - * | - * | <-- br0
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
13 -> - - - - - - - - - - - - - - - * | - * | <-- d0
12 -> - - - - - - - - - - - - - - * - | - * | <-- d1
11 -> - - - - - - - - - - - - - * - - | - * | <-- d2
9 -> - - - - - - - - - - - - * - - - | - * | <-- d3
8 -> - - - - - - - - - - - * - - - - | - * | <-- d4
7 -> - - - - - - - - - - * - - - - - | - * | <-- d5
6 -> - - - - - - - - - * - - - - - - | - * | <-- d6
5 -> - - - - - - - - * - - - - - - - | - * | <-- d7
4 -> * * * * * * * * * * * * * * * * | * * | <-- rdy
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\vhdl\poc.rpt
poc
** EQUATIONS **
clk : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
rdy : INPUT;
-- Node name is ':37' = 'br0'
-- Equation name is 'br0', location is LC032, type is buried.
br0 = DFFE( _EQ001 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = br0 & rdy
# d0 & !rdy;
-- Node name is ':36' = 'br1'
-- Equation name is 'br1', location is LC025, type is buried.
br1 = DFFE( _EQ002 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = br1 & rdy
# d1 & !rdy;
-- Node name is ':35' = 'br2'
-- Equation name is 'br2', location is LC029, type is buried.
br2 = DFFE( _EQ003 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = br2 & rdy
# d2 & !rdy;
-- Node name is ':34' = 'br3'
-- Equation name is 'br3', location is LC026, type is buried.
br3 = DFFE( _EQ004 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = br3 & rdy
# d3 & !rdy;
-- Node name is ':33' = 'br4'
-- Equation name is 'br4', location is LC027, type is buried.
br4 = DFFE( _EQ005 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = br4 & rdy
# d4 & !rdy;
-- Node name is ':32' = 'br5'
-- Equation name is 'br5', location is LC028, type is buried.
br5 = DFFE( _EQ006 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = br5 & rdy
# d5 & !rdy;
-- Node name is ':31' = 'br6'
-- Equation name is 'br6', location is LC030, type is buried.
br6 = DFFE( _EQ007 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = br6 & rdy
# d6 & !rdy;
-- Node name is ':30' = 'br7'
-- Equation name is 'br7', location is LC031, type is buried.
br7 = DFFE( _EQ008 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = br7 & rdy
# d7 & !rdy;
-- Node name is 'pd0' = ':27'
-- Equation name is 'pd0', type is output
pd0 = DFFE( _EQ009 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = br0 & rdy
# pd0 & !rdy;
-- Node name is 'pd1' = ':25'
-- Equation name is 'pd1', type is output
pd1 = DFFE( _EQ010 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = br1 & rdy
# pd1 & !rdy;
-- Node name is 'pd2' = ':23'
-- Equation name is 'pd2', type is output
pd2 = DFFE( _EQ011 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = br2 & rdy
# pd2 & !rdy;
-- Node name is 'pd3' = ':21'
-- Equation name is 'pd3', type is output
pd3 = DFFE( _EQ012 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = br3 & rdy
# pd3 & !rdy;
-- Node name is 'pd4' = ':19'
-- Equation name is 'pd4', type is output
pd4 = DFFE( _EQ013 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = br4 & rdy
# pd4 & !rdy;
-- Node name is 'pd5' = ':17'
-- Equation name is 'pd5', type is output
pd5 = DFFE( _EQ014 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = br5 & rdy
# pd5 & !rdy;
-- Node name is 'pd6' = ':15'
-- Equation name is 'pd6', type is output
pd6 = DFFE( _EQ015 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = br6 & rdy
# pd6 & !rdy;
-- Node name is 'pd7' = ':13'
-- Equation name is 'pd7', type is output
pd7 = DFFE( _EQ016 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = br7 & rdy
# pd7 & !rdy;
-- Node name is 'tr' = ':11'
-- Equation name is 'tr', type is output
tr = DFFE( _EQ017 $ rdy, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = !rdy & tr;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information f:\vhdl\poc.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,937K
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