📄 poc.rpt
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Project Information f:\vhdl\poc.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/19/2007 00:11:31
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
POC
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
poc EPM7032LC44-6 10 9 0 17 0 53 %
User Pins: 10 9 0
Project Information f:\vhdl\poc.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Line 24: File f:\vhdl\poc.vhd: Found multiple assignments to the same signal or signal bit "sr7" in a Process Statement -- only the last assignment will take effect
Project Information f:\vhdl\poc.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Device-Specific Information: f:\vhdl\poc.rpt
poc
***** Logic for device 'poc' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
r V G G G c G p p
d d d C N N N l N d d
6 7 y C D D D k D 7 6
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
d5 | 7 39 | pd5
d4 | 8 38 | pd4
d3 | 9 37 | pd3
GND | 10 36 | pd0
d2 | 11 35 | VCC
d1 | 12 EPM7032LC44-6 34 | pd2
d0 | 13 33 | pd1
RESERVED | 14 32 | RESERVED
VCC | 15 31 | RESERVED
RESERVED | 16 30 | GND
tr | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R R
E E E E N C E E E E E
S S S S D C S S S S S
E E E E E E E E E
R R R R R R R R R
V V V V V V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: f:\vhdl\poc.rpt
poc
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 1/16( 6%) 10/16( 62%) 0/16( 0%) 2/36( 5%)
B: LC17 - LC32 16/16(100%) 8/16( 50%) 0/16( 0%) 25/36( 69%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 18/32 ( 56%)
Total logic cells used: 17/32 ( 53%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 17/32 ( 53%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 3.94
Total fan-in: 67
Total input pins required: 10
Total output pins required: 9
Total bidirectional pins required: 0
Total logic cells required: 17
Total flipflops required: 17
Total product terms required: 34
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: f:\vhdl\poc.rpt
poc
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 clk
13 (9) (A) INPUT 0 0 0 0 0 0 1 d0
12 (8) (A) INPUT 0 0 0 0 0 0 1 d1
11 (7) (A) INPUT 0 0 0 0 0 0 1 d2
9 (6) (A) INPUT 0 0 0 0 0 0 1 d3
8 (5) (A) INPUT 0 0 0 0 0 0 1 d4
7 (4) (A) INPUT 0 0 0 0 0 0 1 d5
6 (3) (A) INPUT 0 0 0 0 0 0 1 d6
5 (2) (A) INPUT 0 0 0 0 0 0 1 d7
4 (1) (A) INPUT 0 0 0 0 0 9 8 rdy
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\vhdl\poc.rpt
poc
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
36 22 B FF + t 0 0 0 1 2 1 0 pd0
33 24 B FF + t 0 0 0 1 2 1 0 pd1
34 23 B FF + t 0 0 0 1 2 1 0 pd2
37 21 B FF + t 0 0 0 1 2 1 0 pd3
38 20 B FF + t 0 0 0 1 2 1 0 pd4
39 19 B FF + t 0 0 0 1 2 1 0 pd5
40 18 B FF + t 0 0 0 1 2 1 0 pd6
41 17 B FF + t 0 0 0 1 2 1 0 pd7
17 12 A FF + t 0 0 0 1 1 1 0 tr
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\vhdl\poc.rpt
poc
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(25) 31 B DFFE + t 0 0 0 2 1 1 1 br7 (:30)
(26) 30 B DFFE + t 0 0 0 2 1 1 1 br6 (:31)
(28) 28 B DFFE + t 0 0 0 2 1 1 1 br5 (:32)
(29) 27 B DFFE + t 0 0 0 2 1 1 1 br4 (:33)
(31) 26 B DFFE + t 0 0 0 2 1 1 1 br3 (:34)
(27) 29 B DFFE + t 0 0 0 2 1 1 1 br2 (:35)
(32) 25 B DFFE + t 0 0 0 2 1 1 1 br1 (:36)
(24) 32 B DFFE + t 0 0 0 2 1 1 1 br0 (:37)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\vhdl\poc.rpt
poc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC12 tr
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B | Logic cells that feed LAB 'A':
LC12 -> * | * - | <-- tr
Pin
43 -> - | - - | <-- clk
4 -> * | * * | <-- rdy
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\vhdl\poc.rpt
poc
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
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