it is a plural multiplication,use VHDL language compile.

9x8复数乘法混频器VHDL
     Library IEEE;
     Use ieee.std_logic_1164.all;
     Use ieee.std_logic_arith.all;
       Entity ccmul is
           Generic(w2  :integer:=17;  乘积字节宽
           W1: integer:=9;  扩展字节宽
           w: integer:=8;  输入数据字节宽
            ）； 
           Port(x_in:in std_logic_vector(w-1 downto 0);
               y_in:in std_logic_vector(w-1 downto 0);
               cos_in:in std_logic_vector(w-1 downto 0);
               cps_in:in std_logic_vector(w1-1 downto 0);   
               cms_in:in std_logic_vector(w1-1 downto 0);
               r_out:out std_logic_vector(w downto 0);
               i_out:out std_logic_vector(w downto 0));
             end ccmul;
           Architecture arch_ccmul of ccmul is 
              signal cps,cms :std_logic_vector(w1-1 downto 0);
              signal x,y,cos :std_logic_vector(w-1 downto 0);
              signal xmy :std_logic_vector(w1-1 downto 0);
              signal z,csy,csx :std_logic_vector(w2-1 downto 0);
              signal r,i :std_logic_vector(w2-1 downto 0);
            Function ssplus(                
                    X1 :std_logic_vector(w-1 downto 0);
                    x2 :std_logic_vector(w-1 downto 0));       8bit 加法器
                    return std_logic_vector is
                    vriable y :std_logic_vector(w-1 downto 0);
                    vriable plus :std_logic_vector(w-1 downto 0);
                    begin 
                       plus :=x1+x2;
                       if (x1(x1`high)/=x2(x2`high)) then
y:=plus(plus`high )&`0`& plus(w-2 downto 0);
else
                           y:=x1(x1`high)+
                       end if;
                     return y;
                   end ssplus;
              Function ssminu(
                     x1 :std_logic_vector(w-1 downto 0);
                     x2 :std_logic_vector(w-1 downto 0));    8BIT 减法器
                    return std_logic_vector is
                    vriable x3 :std_logic_vector(w-1 downto 0);
                    vriable y :std_logic_vector(w-1 downto 0);
                    vriable plus :std_logic_vector(w-1 downto 0);
                    begin 
                       x3:=not(x2)+1;
                       plus :=x1+x3;
                       if (x1(x1`high) =x2(x2`high)) then
y:=plus(plus`high )& plus;
y:=x1(x1`high)+
                       end if;
                     return y;
                   end ssminu;
                   Function ssplus2(
                       X1 :std_logic_vector(w2-1 downto 0);
                       x2 :std_logic_vector(w2-1 downto 0));       17bit 加法器
                       return std_logic_vector is
                       vriable y :std_logic_vector(w2-1 downto 0);
                       vriable plus :std_logic_vector(w2-1 downto 0);
                       begin 
                          plus :=x1+x2;
                       return plus;
                     end ssplus2;
                    Function ssminu2(
                     x1 :std_logic_vector(w2-1 downto 0);
                     x2 :std_logic_vector(w2-1 downto 0));    17BIT 减法器
                    return std_logic_vector is
                    vriable x3 :std_logic_vector(w2-1 downto 0);
                    vriable y :std_logic_vector(w2-1 downto 0);
                    vriable plus :std_logic_vector(w2-1 downto 0);
                    begin 
                       x3:=not(x2)+1;
                       plus :=x1+x3;
                       return plus;
                       end ssminu2;
                     Function ssmul(
                          X1 :std_logic_vector(w-1 downto 0);
                          x2 :std_logic_vector(w-1 downto 0));       9bit*8bit 乘法器
                          return std_logic_vector is
                          vriable y :std_logic_vector(w2-1 downto 0);
                          vriable expx1 :std_logic_vector(w1-1 downto 0);
                          vriable expx2 :std_logic_vector(w-1 downto 0);
                          vriable mul :std_logic_vector(w2-1 downto 0);
                          begin                             
if (x1(x1`high) = `1` ) then
expx1:=not((`1`&`0`& x1(w1-2 downto 0))-1);
else
    expx1:=x1;
 end if;
if(x2(x2`high)=`1` then
     expx2:=not((`1`& x2(w-2 downto 0))-1);
   else
     expx2:=x2;
end if;
mul:=expx1*expx2;
if (x1(x1`high)/=x2(x2`high)) then
    y:=not(mul)+1;
 else
    y:=mul;
                            end if;
                            return y;
                            end ssmul;
                    begin
                       x<=x_in;
                       y<=y_in;
                       cos<=cos_in;
                       cps<=cps_in;
                       cms<=cms_in;
                       xmy<=ssminu(x,y);
                       z<=ssmul(xmy,cos);
                       csy<=ssmul(cms,y);
                       r<=ssplus2(csy,z);
                       csx<=ssmul(cps,x);
                       i<=ssminu2(csx,z);
                       r_out<=r(w2-2 downto w-1);
                       i_out<=i(w2-2 downto w-1);
                    end architecture;