mx2.h

mx21 Nor flash Bootloader 源代码

#ifndef INC_MX2
#define INC_MX2

//#define DEBUG

#include "type.h"

#define SYS_BASE_ADDR	      	0x10027800	
#define SYS_SIDR	      	(SYS_BASE_ADDR+0x10)	//;  128bit Silicon ID Reg
#define SYS_FMCR	      	(SYS_BASE_ADDR+0x14)	//;  Functional Muxing Control Reg
#define SYS_GPCR	      	(SYS_BASE_ADDR+0x18)	//;  Global Peripheral Control Reg
#define SYS_WBCR	      	(SYS_BASE_ADDR+0x1C)	//;  Well Bias Control Reg
#define SYS_DSCR1	      	(SYS_BASE_ADDR+0x20)	//;  Drive Strength Crtl Reg 1
#define SYS_DSCR2	      	(SYS_BASE_ADDR+0x24)	//;  Drive Strength Crtl Reg 2
#define SYS_DSCR3	      	(SYS_BASE_ADDR+0x28)	//;  Drive Strength Crtl Reg 3
#define SYS_DSCR4	      	(SYS_BASE_ADDR+0x2C)	//;  Drive Strength Crtl Reg 4
#define SYS_DSCR5	      	(SYS_BASE_ADDR+0x30)	//;  Drive Strength Crtl Reg 5
#define SYS_DSCR6	      	(SYS_BASE_ADDR+0x34)	//;  Drive Strength Crtl Reg 6
#define SYS_DSCR7	      	(SYS_BASE_ADDR+0x38)	//;  Drive Strength Crtl Reg 7
#define SYS_DSCR8	      	(SYS_BASE_ADDR+0x3C)	//;  Drive Strength Crtl Reg 8
#define SYS_DSCR9	      	(SYS_BASE_ADDR+0x40)	//;  Drive Strength Crtl Reg 9
#define SYS_DSCR10	      	(SYS_BASE_ADDR+0x44)	//;  Drive Strength Crtl Reg 10
#define SYS_DSCR11	      	(SYS_BASE_ADDR+0x48)	//;  Drive Strength Crtl Reg 11
#define SYS_DSCR12	      	(SYS_BASE_ADDR+0x4C)	//;  Drive Strength Crtl Reg 12
#define SYS_PSCR	      	(SYS_BASE_ADDR+0x50)	//;  Priority Control/select Reg


#define GPIOA	0
#define GPIOB	1
#define GPIOC	2
#define GPIOD	3
#define GPIOE	4
#define GPIOF	5

/* Use as GPIO_BASE_ADDR(GPIOA)- GPIO_BASE_ADDR(GPIOF)*/
#define GPIO_BASE_ADDR(x)	(0x10015000+x*0x100)
	
#define _reg_GPIO_DDIR(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x00)))  //  32bit gpio pta data direction reg
#define _reg_GPIO_OCR1(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x04)))  //  32bit gpio pta output config 1 reg
#define _reg_GPIO_OCR2(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x08)))  //  32bit gpio pta output config 2 reg
#define _reg_GPIO_ICONFA1(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x0C)))  //  32bit gpio pta input config A1 reg
#define _reg_GPIO_ICONFA2(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x10)))  //  32bit gpio pta input config A2 reg
#define _reg_GPIO_ICONFB1(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x14)))  //  32bit gpio pta input config B1 reg
#define _reg_GPIO_ICONFB2(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x18)))  //  32bit gpio pta input config B2 reg
#define _reg_GPIO_DR(x)		(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x1C)))  //  32bit gpio pta data reg
#define _reg_GPIO_GIUS(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x20)))  //  32bit gpio pta in use reg
#define _reg_GPIO_SSR(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x24)))  //  32bit gpio pta sample status reg
#define _reg_GPIO_ICR1(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x28)))  //  32bit gpio pta interrupt ctrl 1 reg
#define _reg_GPIO_ICR2(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x2C)))  //  32bit gpio pta interrupt ctrl 2 reg
#define _reg_GPIO_IMR(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x30)))  //  32bit gpio pta interrupt mask reg
#define _reg_GPIO_ISR(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x34)))  //  32bit gpio pta interrupt status reg
#define _reg_GPIO_GPR(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x38)))  //  32bit gpio pta general purpose reg
#define _reg_GPIO_SWR(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x3C)))  //  32bit gpio pta software reset reg
#define _reg_GPIO_PUEN(x)	(*((volatile unsigned long *)(GPIO_BASE_ADDR(x)+0x40)))  //  32bit gpio pta pull up enable reg

//#########################################		
//# WEIM                                  #		
//# $DF00_1000 to $DF00_1FFF              #		
//#########################################		
#define CS0	0
#define CS1	1
#define CS2	2
#define CS3	3
#define CS4	4
#define CS5	5

#define MX2ADS_EMI_BASE             	0xDF001000

#define _reg_WEIM_CSU(x)	(*((volatile unsigned long *)(MX2ADS_EMI_BASE+4*x)))  //  32bit eim chip sel 0 upper ctr reg
#define _reg_WEIM_CSL(x)	(*((volatile unsigned long *)(MX2ADS_EMI_BASE+0x04+4*x)))  //  32bit eim chip sel 0 lower ctr reg


#define AITC_BASE_ADDR	0x10040000	
#define _reg_AITC_INTCNTL	(*((volatile unsigned long *)(AITC_BASE_ADDR)))  //  32bit aitc int control reg
#define _reg_AITC_NIMASK	(*((volatile unsigned long *)(AITC_BASE_ADDR+0x04)))  //  32bit aitc int mask reg
#define _reg_AITC_INTENNUM	(*((volatile unsigned long *)(AITC_BASE_ADDR+0x08)))  //  32bit aitc int enable number reg
#define _reg_AITC_INTDISNUM	(*((volatile unsigned long *)(AITC_BASE_ADDR+0x0C)))  //  32bit aitc int disable number reg
#define _reg_AITC_INTENABLEH	(*((volatile unsigned long *)(AITC_BASE_ADDR+0x10)))  //  32bit aitc int enable reg high
#define _reg_AITC_INTENABLEL	(*((volatile unsigned long *)(AITC_BASE_ADDR+0x14)))  //  32bit aitc int enable reg low
#define _reg_AITC_INTTYPEH	(*((volatile unsigned long *)(AITC_BASE_ADDR+0x18)))  //  32bit aitc int type reg high
#define _reg_AITC_INTTYPEL	(*((volatile unsigned long *)(AITC_BASE_ADDR+0x1C)))  //  32bit aitc int type reg low

// PLL
#define CRM_BASE_ADDR	0x10027000	
#define _reg_CRM_CSCR		(*((volatile unsigned long *)(CRM_BASE_ADDR+0x00)))  //  32bit Clock Source Control Reg
#define _reg_CRM_MPCTL0		(*((volatile unsigned long *)(CRM_BASE_ADDR+0x04)))  //  32bit MCU PLL Control Reg
#define _reg_CRM_MPCTL1		(*((volatile unsigned long *)(CRM_BASE_ADDR+0x08)))  //  32bit MCU PLL 
#define _reg_CRM_SPCTL0		(*((volatile unsigned long *)(CRM_BASE_ADDR+0x0C)))  //  32bit Serial Perpheral PLL Ctrl 0
#define _reg_CRM_SPCTL1		(*((volatile unsigned long *)(CRM_BASE_ADDR+0x10)))  //  32bit Serial Perpheral PLL Ctrl 1
#define _reg_CRM_OSC26MCTL	(*((volatile unsigned long *)(CRM_BASE_ADDR+0x14)))  //  32bit Osc 26M register
#define _reg_CRM_PCDR		(*((volatile unsigned long *)(CRM_BASE_ADDR+0x18)))  //  32bit Serial Perpheral Clk Div Reg
#define _reg_CRM_PCCR0		(*((volatile unsigned long *)(CRM_BASE_ADDR+0x1C)))  //  32bit Perpheral Clk Control Reg 0
#define _reg_CRM_PCCR1		(*((volatile unsigned long *)(CRM_BASE_ADDR+0x20)))  //  32bit Perpheral Clk Control Reg 1


// SDRAM controller registers
#define SDRC_BASE           0xDF000000
#define _reg_SDRC_SDCTL0    (*((volatile U32 *)(SDRC_BASE+0x00)))
#define _reg_SDRC_SDCTL1    (*((volatile U32 *)(SDRC_BASE+0x04)))


#define _reg_PLL_PCDR    (*((volatile U32 *)(0x0021b020)))

//#########################################		
//# AIPI1                                 #		
//# $1000_0000 to $1000_0FFF              #		
//#########################################		
#define AIPI1_BASE_ADDR	0x10000000	
#define _reg_AIPI1_PSR0		(*((volatile unsigned long *)(AIPI1_BASE_ADDR+0x00)))	//  32bit Peripheral Size Reg 0
#define _reg_AIPI1_PSR1		(*((volatile unsigned long *)(AIPI1_BASE_ADDR+0x04)))	//  32bit Peripheral Size Reg 1
#define _reg_AIPI1_PAR		(*((volatile unsigned long *)(AIPI1_BASE_ADDR+0x08)))	//  32bit Peripheral Access Reg

//#########################################		
//# AIPI2                                 #		
//# $1002_0000 to $1002_0FFF              #		
//#########################################		
#define AIPI2_BASE_ADDR	0x10020000	
#define _reg_AIPI2_PSR0		(*((volatile unsigned long *)(AIPI2_BASE_ADDR+0x00)))  //  32bit Peripheral Size Reg 0
#define _reg_AIPI2_PSR1		(*((volatile unsigned long *)(AIPI2_BASE_ADDR+0x04)))  //  32bit Peripheral Size Reg 1
#define _reg_AIPI2_PAR		(*((volatile unsigned long *)(AIPI2_BASE_ADDR+0x08)))  //  32bit Peripheral Access Reg


/* 
since mx2 use usb-otg, we don't need it here
*/

#define USBD_BASE						0x00212000
#define _reg_USBD_STAT				(*((volatile U32 *)(USBD_BASE+0x008)))
#define _reg_USBD_CTRL				(*((volatile U32 *)(USBD_BASE+0x00C)))
#define _reg_USBD_CFGBSY			(*((volatile U32 *)(USBD_BASE+0x010)))
#define _reg_USBD_EPBUF				(*((volatile U32 *)(USBD_BASE+0x014)))
#define _reg_USBD_INTR_STAT		(*((volatile U32 *)(USBD_BASE+0x018)))
#define _reg_USBD_INTR_MASK		(*((volatile U32 *)(USBD_BASE+0x01C)))
#define _reg_USBD_ENABLE			(*((volatile U32 *)(USBD_BASE+0x024)))
#define _reg_USBD_EP0_STAT			(*((volatile U32 *)(USBD_BASE+0x030)))
#define _reg_USBD_EP0_INTR_STAT	(*((volatile U32 *)(USBD_BASE+0x034)))
#define _reg_USBD_EP0_INTR_MASK	(*((volatile U32 *)(USBD_BASE+0x038)))
#define _reg_USBD_EP0_FDAT			(*((volatile U32 *)(USBD_BASE+0x03C)))
#define _reg_USBD_EP0_FCTRL		(*((volatile U32 *)(USBD_BASE+0x044)))
#define _reg_USBD_EP0_FALRM		(*((volatile U32 *)(USBD_BASE+0x050)))
#define _reg_USBD_EP1_STAT			(*((volatile U32 *)(USBD_BASE+0x060)))
#define _reg_USBD_EP1_INTR_STAT	(*((volatile U32 *)(USBD_BASE+0x064)))
#define _reg_USBD_EP1_INTR_MASK	(*((volatile U32 *)(USBD_BASE+0x068)))
#define _reg_USBD_EP1_FDAT			(*((volatile U32 *)(USBD_BASE+0x06C)))
#define _reg_USBD_EP1_FCTRL		(*((volatile U32 *)(USBD_BASE+0x074)))
#define _reg_USBD_EP1_FALRM		(*((volatile U32 *)(USBD_BASE+0x080)))
#define _reg_USBD_EP2_STAT			(*((volatile U32 *)(USBD_BASE+0x090)))
#define _reg_USBD_EP2_INTR_STAT	(*((volatile U32 *)(USBD_BASE+0x094)))
#define _reg_USBD_EP2_INTR_MASK	(*((volatile U32 *)(USBD_BASE+0x098)))
#define _reg_USBD_EP2_FDAT			(*((volatile U32 *)(USBD_BASE+0x09C)))
#define _reg_USBD_EP2_FCTRL		(*((volatile U32 *)(USBD_BASE+0x0A4)))
#define _reg_USBD_EP2_FALRM		(*((volatile U32 *)(USBD_BASE+0x0B0)))
#define _reg_USBD_EP3_STAT			(*((volatile U32 *)(USBD_BASE+0x0C0)))
#define _reg_USBD_EP3_INTR_STAT	(*((volatile U32 *)(USBD_BASE+0x0C4)))
#define _reg_USBD_EP3_INTR_MASK	(*((volatile U32 *)(USBD_BASE+0x0C8)))
#define _reg_USBD_EP3_FDAT			(*((volatile U32 *)(USBD_BASE+0x0CC)))
#define _reg_USBD_EP3_FCTRL		(*((volatile U32 *)(USBD_BASE+0x0D4)))
#define _reg_USBD_EP3_FALRM		(*((volatile U32 *)(USBD_BASE+0x0E0)))
#define _reg_USBD_EP4_STAT			(*((volatile U32 *)(USBD_BASE+0x0F0)))
#define _reg_USBD_EP4_INTR_STAT	(*((volatile U32 *)(USBD_BASE+0x0F4)))
#define _reg_USBD_EP4_INTR_MASK	(*((volatile U32 *)(USBD_BASE+0x0F8)))
#define _reg_USBD_EP4_FDAT			(*((volatile U32 *)(USBD_BASE+0x0FC)))
#define _reg_USBD_EP4_FCTRL		(*((volatile U32 *)(USBD_BASE+0x104)))
#define _reg_USBD_EP4_FALRM		(*((volatile U32 *)(USBD_BASE+0x110)))
#define _reg_USBD_EP5_STAT			(*((volatile U32 *)(USBD_BASE+0x120)))
#define _reg_USBD_EP5_INTR_STAT	(*((volatile U32 *)(USBD_BASE+0x124)))
#define _reg_USBD_EP5_INTR_MASK	(*((volatile U32 *)(USBD_BASE+0x128)))
#define _reg_USBD_EP5_FDAT			(*((volatile U32 *)(USBD_BASE+0x12C)))
#define _reg_USBD_EP5_FCTRL		(*((volatile U32 *)(USBD_BASE+0x134)))
#define _reg_USBD_EP5_FALRM		(*((volatile U32 *)(USBD_BASE+0x140)))

#define MDEVREQ_MASK					0x00000008
#define EOT_MASK						0x00000004
#define DEVREQ_MASK					0x00000002
#define EOF_MASK						0x00000001
#define WFR_MASK						0x20000000
#define CMD_OVER_MASK				0x00000040
#define SOF_MASK						0x00000040
#define RST_STOP_MASK				0x00000020
#define RST_START_MASK				0x00000010
#define CFG_CHG_MASK					0x00000001
#define ZLPS_MASK						0x00000004
#define FORCE_STALL_MASK			0x00000001
// PLAM
#define USB_DIV_MASK				0x1C000000
// end PLAM




#endif