tahiti_def.h

mx21 Nor flash Bootloader 源代码

#define GPIOC_ICR2	      (GPIOC_BASE_ADDR+0x2C)   //  32bit gpio ptc interrupt ctrl 2 reg
#define GPIOC_IMR	      (GPIOC_BASE_ADDR+0x30)   //  32bit gpio ptc interrupt mask reg
#define GPIOC_ISR	      (GPIOC_BASE_ADDR+0x34)   //  32bit gpio ptc interrupt status reg
#define GPIOC_GPR	      (GPIOC_BASE_ADDR+0x38)   //  32bit gpio ptc general purpose reg
#define GPIOC_SWR	      (GPIOC_BASE_ADDR+0x3C)   //  32bit gpio ptc software reset reg 
#define GPIOC_PUEN	      (GPIOC_BASE_ADDR+0x40)   //  32bit gpio ptc pull up enable reg
			
#define GPIOD_BASE_ADDR	       	0x10015300	
#define GPIOD_DDIR	      (GPIOD_BASE_ADDR+0x00)   //  32bit gpio ptd data direction reg
#define GPIOD_OCR1	      (GPIOD_BASE_ADDR+0x04)   //  32bit gpio ptd output config 1 reg
#define GPIOD_OCR2	      (GPIOD_BASE_ADDR+0x08)   //  32bit gpio ptd output config 2 reg
#define GPIOD_ICONFA1	      (GPIOD_BASE_ADDR+0x0C)   //  32bit gpio ptd input config A1 reg
#define GPIOD_ICONFA2	      (GPIOD_BASE_ADDR+0x10)   //  32bit gpio ptd input config A2 reg
#define GPIOD_ICONFB1	      (GPIOD_BASE_ADDR+0x14)   //  32bit gpio ptd input config B1 reg
#define GPIOD_ICONFB2	      (GPIOD_BASE_ADDR+0x18)   //  32bit gpio ptd input config B2 reg
#define GPIOD_DR	      (GPIOD_BASE_ADDR+0x1C)   //  32bit gpio ptd data reg
#define GPIOD_GIUS	      (GPIOD_BASE_ADDR+0x20)   //  32bit gpio ptd in use reg
#define GPIOD_SSR	      (GPIOD_BASE_ADDR+0x24)   //  32bit gpio ptd sample status reg
#define GPIOD_ICR1	      (GPIOD_BASE_ADDR+0x28)   //  32bit gpio ptd interrupt ctrl 1 reg
#define GPIOD_ICR2	      (GPIOD_BASE_ADDR+0x2C)   //  32bit gpio ptd interrupt ctrl 2 reg
#define GPIOD_IMR	      (GPIOD_BASE_ADDR+0x30)   //  32bit gpio ptd interrupt mask reg
#define GPIOD_ISR	      (GPIOD_BASE_ADDR+0x34)   //  32bit gpio ptd interrupt status reg
#define GPIOD_GPR	      (GPIOD_BASE_ADDR+0x38)   //  32bit gpio ptd general purpose reg
#define GPIOD_SWR	      (GPIOD_BASE_ADDR+0x3C)   //  32bit gpio ptd software reset reg 
#define GPIOD_PUEN	      (GPIOD_BASE_ADDR+0x40)   //  32bit gpio ptd pull up enable reg
			
#define GPIOE_BASE_ADDR	       	0x10015400	
#define GPIOE_DDIR	      (GPIOE_BASE_ADDR+0x00)   //  32bit gpio pte data direction reg
#define GPIOE_OCR1	      (GPIOE_BASE_ADDR+0x04)   //  32bit gpio pte output config 1 reg
#define GPIOE_OCR2	      (GPIOE_BASE_ADDR+0x08)   //  32bit gpio pte output config 2 reg
#define GPIOE_ICONFA1	      (GPIOE_BASE_ADDR+0x0C)   //  32bit gpio pte input config A1 reg
#define GPIOE_ICONFA2	      (GPIOE_BASE_ADDR+0x10)   //  32bit gpio pte input config A2 reg
#define GPIOE_ICONFB1	      (GPIOE_BASE_ADDR+0x14)   //  32bit gpio pte input config B1 reg
#define GPIOE_ICONFB2	      (GPIOE_BASE_ADDR+0x18)   //  32bit gpio pte input config B2 reg
#define GPIOE_DR	      (GPIOE_BASE_ADDR+0x1C)   //  32bit gpio pte data reg
#define GPIOE_GIUS	      (GPIOE_BASE_ADDR+0x20)   //  32bit gpio pte in use reg
#define GPIOE_SSR	      (GPIOE_BASE_ADDR+0x24)   //  32bit gpio pte sample status reg
#define GPIOE_ICR1	      (GPIOE_BASE_ADDR+0x28)   //  32bit gpio pte interrupt ctrl 1 reg
#define GPIOE_ICR2	      (GPIOE_BASE_ADDR+0x2C)   //  32bit gpio pte interrupt ctrl 2 reg
#define GPIOE_IMR	      (GPIOE_BASE_ADDR+0x30)   //  32bit gpio pte interrupt mask reg
#define GPIOE_ISR	      (GPIOE_BASE_ADDR+0x34)   //  32bit gpio pte interrupt status reg
#define GPIOE_GPR	      (GPIOE_BASE_ADDR+0x38)   //  32bit gpio pte general purpose reg
#define GPIOE_SWR	      (GPIOE_BASE_ADDR+0x3C)   //  32bit gpio pte software reset reg 
#define GPIOE_PUEN	      (GPIOE_BASE_ADDR+0x40)   //  32bit gpio pte pull up enable reg
			
#define GPIOF_BASE_ADDR	       	0x10015500	
#define GPIOF_DDIR	      (GPIOF_BASE_ADDR+0x00)   //  32bit gpio ptf data direction reg
#define GPIOF_OCR1	      (GPIOF_BASE_ADDR+0x04)   //  32bit gpio ptf output config 1 reg
#define GPIOF_OCR2	      (GPIOF_BASE_ADDR+0x08)   //  32bit gpio ptf output config 2 reg
#define GPIOF_ICONFA1	      (GPIOF_BASE_ADDR+0x0C)   //  32bit gpio ptf input config A1 reg
#define GPIOF_ICONFA2	      (GPIOF_BASE_ADDR+0x10)   //  32bit gpio ptf input config A2 reg
#define GPIOF_ICONFB1	      (GPIOF_BASE_ADDR+0x14)   //  32bit gpio ptf input config B1 reg
#define GPIOF_ICONFB2	      (GPIOF_BASE_ADDR+0x18)   //  32bit gpio ptf input config B2 reg
#define GPIOF_DR	      (GPIOF_BASE_ADDR+0x1C)   //  32bit gpio ptf data reg
#define GPIOF_GIUS	      (GPIOF_BASE_ADDR+0x20)   //  32bit gpio ptf in use reg
#define GPIOF_SSR	      (GPIOF_BASE_ADDR+0x24)   //  32bit gpio ptf sample status reg
#define GPIOF_ICR1	      (GPIOF_BASE_ADDR+0x28)   //  32bit gpio ptf interrupt ctrl 1 reg
#define GPIOF_ICR2	      (GPIOF_BASE_ADDR+0x2C)   //  32bit gpio ptf interrupt ctrl 2 reg
#define GPIOF_IMR	      (GPIOF_BASE_ADDR+0x30)   //  32bit gpio ptf interrupt mask reg
#define GPIOF_ISR	      (GPIOF_BASE_ADDR+0x34)   //  32bit gpio ptf interrupt status reg
#define GPIOF_GPR	      (GPIOF_BASE_ADDR+0x38)   //  32bit gpio ptf general purpose reg
#define GPIOF_SWR	      (GPIOF_BASE_ADDR+0x3C)   //  32bit gpio ptf software reset reg 
#define GPIOF_PUEN	      (GPIOF_BASE_ADDR+0x40)   //  32bit gpio ptf pull up enable reg
			
#define GPIO_REG_BASE	       	0x10015600	
#define GPIO_PMASK	      (GPIO_REG_BASE+0x00)   //  32bit gpio interrupt mask reg


//;#########################################			
//;# AIPI2                                 #			
//;# $1002_0000 to $1002_0FFF              #			
//;#########################################			
#define AIPI2_BASE_ADDR	      	0x10020000	
#define AIPI2_PSR0	      	(AIPI2_BASE_ADDR+0x00)	//  32bit Peripheral Size Reg 0
#define AIPI2_PSR1	      	(AIPI2_BASE_ADDR+0x04)	//  32bit Peripheral Size Reg 1
#define AIPI2_PAR	      	(AIPI2_BASE_ADDR+0x08)	//  32bit Peripheral Access Reg



// ;#########################################			
// ;# USBOTG                                #			
// ;# $1002_4000 to $1002_5FFF              #			
// ;#########################################			
#define OTG_BASE_ADDR	       	0x10024000	
#define OTG_CORE_BASE	       	(OTG_BASE_ADDR+0x000)		//  base location for core
#define OTG_FUNC_BASE	       	(OTG_BASE_ADDR+0x040)		//  base location for function
#define OTG_HOST_BASE	       	(OTG_BASE_ADDR+0x080)		//  base location for host
#define OTG_DMA_BASE	       	(OTG_BASE_ADDR+0x800)		//  base location for dma
#define OTG_I2C_BASE		OTG_BASE_ADDR+0x100


			
#define OTG_ETD_BASE	       	(OTG_BASE_ADDR+0x200)		//  base location for etd memory
#define OTG_EP_BASE	       	(OTG_BASE_ADDR+0x400)		//  base location for ep memory
#define OTG_SYS_BASE	       	(OTG_BASE_ADDR+0x600)		//  base location for system
#define OTG_DATA_BASE	       	(OTG_BASE_ADDR+0x1000)	//  base location for data memory

#define OTG_SYS_CTRL	       		(OTG_SYS_BASE+0x000)	//  base location for system
			
#define OTG_CORE_HWMODE	       		(OTG_CORE_BASE+0x00)     //  32bit core hardware mode reg
#define OTG_CORE_CINT_STAT	       	(OTG_CORE_BASE+0x04)     //  32bit core int status reg
#define OTG_CORE_CINT_STEN	       	(OTG_CORE_BASE+0x08)     //  32bit core int enable reg
#define OTG_CORE_CLK_CTRL	       	(OTG_CORE_BASE+0x0C)     //  32bit core clock control reg
#define OTG_CORE_RST_CTRL	       	(OTG_CORE_BASE+0x10)     //  32bit core reset control reg
#define OTG_CORE_FRM_INTVL	       	(OTG_CORE_BASE+0x14)     //  32bit core frame interval reg
#define OTG_CORE_FRM_REMAIN	       	(OTG_CORE_BASE+0x18)     //  32bit core frame remaining reg
#define OTG_CORE_HNP_CSTAT	       	(OTG_CORE_BASE+0x1C)     //  32bit core HNP current state reg
#define OTG_CORE_HNP_TIMER1	       	(OTG_CORE_BASE+0x20)     //  32bit core HNP timer 1 reg
#define OTG_CORE_HNP_TIMER2	       	(OTG_CORE_BASE+0x24)     //  32bit core HNP timer 2 reg
#define OTG_CORE_HNP_T3PCR	       	(OTG_CORE_BASE+0x28)     //  32bit core HNP timer 3 pulse ctrl
#define OTG_CORE_HINT_STAT	       	(OTG_CORE_BASE+0x2C)     //  32bit core HNP int status reg
#define OTG_CORE_HINT_STEN	       	(OTG_CORE_BASE+0x30)     //  32bit core HNP int enable reg
			
#define OTG_FUNC_CND_STAT	       	(OTG_FUNC_BASE+0x00)     //  32bit func command status reg
#define OTG_FUNC_DEV_ADDR	       	(OTG_FUNC_BASE+0x04)     //  32bit func device address reg
#define OTG_FUNC_SINT_STAT	       	(OTG_FUNC_BASE+0x08)     //  32bit func system int status reg
#define OTG_FUNC_SINT_STEN	       	(OTG_FUNC_BASE+0x0C)     //  32bit func system int enable reg
#define OTG_FUNC_XINT_STAT	       	(OTG_FUNC_BASE+0x10)     //  32bit func X buf int status reg
#define OTG_FUNC_YINT_STAT	       	(OTG_FUNC_BASE+0x14)     //  32bit func Y buf int status reg
#define OTG_FUNC_XYINT_STEN	       	(OTG_FUNC_BASE+0x18)     //  32bit func XY buf int enable reg
#define OTG_FUNC_XFILL_STAT	       	(OTG_FUNC_BASE+0x1C)     //  32bit func X filled status reg
#define OTG_FUNC_YFILL_STAT	       	(OTG_FUNC_BASE+0x20)     //  32bit func Y filled status reg
#define OTG_FUNC_EP_EN	       		(OTG_FUNC_BASE+0x24)     //  32bit func endpoints enable reg
#define OTG_FUNC_EP_RDY	       		(OTG_FUNC_BASE+0x28)     //  32bit func endpoints ready reg
#define OTG_FUNC_IINT	       		(OTG_FUNC_BASE+0x2C)     //  32bit func immediate interrupt reg
#define OTG_FUNC_EP_DSTAT	       	(OTG_FUNC_BASE+0x30)     //  32bit func endpoints done status
#define OTG_FUNC_EP_DEN	       		(OTG_FUNC_BASE+0x34)     //  32bit func endpoints done enable
#define OTG_FUNC_EP_TOGGLE	       	(OTG_FUNC_BASE+0x38)     //  32bit func endpoints toggle bits
#define OTG_FUNC_FRM_NUM	       	(OTG_FUNC_BASE+0x3C)     //  32bit func frame number reg
			
#define OTG_HOST_CTRL	       		(OTG_HOST_BASE+0x00)     //  32bit host controller config reg
#define OTG_HOST_SINT_STAT	       	(OTG_HOST_BASE+0x08)     //  32bit host system int status reg
#define OTG_HOST_SINT_STEN	       	(OTG_HOST_BASE+0x0C)     //  32bit host system int enable reg
#define OTG_HOST_XINT_STAT	       	(OTG_HOST_BASE+0x18)     //  32bit host X buf int status reg
#define OTG_HOST_YINT_STAT	       	(OTG_HOST_BASE+0x1C)     //  32bit host Y buf int status reg
#define OTG_HOST_XYINT_STEN	       	(OTG_HOST_BASE+0x20)     //  32bit host XY buf int enable reg
#define OTG_HOST_XFILL_STAT	       	(OTG_HOST_BASE+0x28)     //  32bit host X filled status reg
#define OTG_HOST_YFILL_STAT	       	(OTG_HOST_BASE+0x2C)     //  32bit host Y filled status reg
#define OTG_HOST_ETD_EN	       		(OTG_HOST_BASE+0x40)     //  32bit host ETD enables reg
#define OTG_HOST_DIR_ROUTE	       	(OTG_HOST_BASE+0x48)     //  32bit host direct routing reg
#define OTG_HOST_IINT	       		(OTG_HOST_BASE+0x4C)     //  32bit host immediate interrupt reg
#define OTG_HOST_EP_DSTAT	       	(OTG_HOST_BASE+0x50)     //  32bit host endpoints done status
#define OTG_HOST_ETD_DONE	       	(OTG_HOST_BASE+0x54)     //  32bit host ETD done reg
#define OTG_HOST_FRM_NUM	       	(OTG_HOST_BASE+0x60)     //  32bit host frame number reg
#define OTG_HOST_LSP_THRESH	       	(OTG_HOST_BASE+0x64)     //  32bit host low speed threshold reg
#define OTG_HOST_HUB_DESCA	       	(OTG_HOST_BASE+0x68)     //  32bit host root hub descriptor A
#define OTG_HOST_HUB_DESCB	       	(OTG_HOST_BASE+0x6C)     //  32bit host root hub descriptor B
#define OTG_HOST_HUB_STAT	       	(OTG_HOST_BASE+0x70)     //  32bit host root hub status reg