📄 uart.c
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/// @ingroup AMD_BOOTLOADER/// @file uart.c/// @brief Uart operator function////// @author /// @version $Version$//<<<<<Include#include "uart.h"#include "../Include/mx2.h"#include "../Include/Tahiti_def.h"//>>>>>Include//<<<<<< Private Macro//>>>>>> Private Macro//<<<<<< Private Structure//>>>>>> Private Structure//<<<<<< Global Variable//>>>>>> Global Variable//<<<<<Private Function Declearation//>>>>>Private Function Declearation//<<<<<Body///Config Mx21 Uart1 Clockvoid MX21_UartSetting(void){ U32 temp; //only config MPCTL0 and poll the MPLLRESTART when FMCR [31:30] (CLKMODE[1:0]) = b11/b01/b10 // PLL non bypass mode if (*(VP_U32)SYS_FMCR & 0xC0000000) { // 266MHz/ (1 [PRESC = b00, /1] * 3 [BCLKDIV=b0010, /3] * 2 [IPDIV=b1, /2]) // HCLK = 88MHz FLCK = 266MHz // { changed for TO2 temp = *(VP_U32)CRM_CSCR; temp |= 0x60000000; *(VP_U32)CRM_CSCR = temp; //set PRESC = b11 (i.e. /4) will change to /2 later// changed for TO2 } temp = *(VP_U32)CRM_CSCR; temp |= 0x00000200; *(VP_U32)CRM_CSCR = temp; //set IPDIV = 1 temp = *(VP_U32)CRM_CSCR; temp &= ~0x00003C00;//modify it temp |= 0x00000400; // set BCLKDIV = 1 (i.e. /2) // temp |= 0x00000800; // set BCLKDIV = 2 (i.e. /3) //end *(VP_U32)CRM_CSCR = temp; //PLL input 32.768kHz //PD = 0, MFD = 312, MFI = 7, MFN=197, PLL Output Frequency =255.9999476MHz//modify it// *(VP_U32)CRM_MPCTL0 = 0x01381CC5; //256M *(VP_U32)CRM_MPCTL0 = 0x007b1C73; //266M//end *(VP_U32)CRM_CSCR |=0x00200000; //wait for the MPLLRESTART bit self clear while (*(VP_U32)CRM_CSCR & 0x00200000);// { Changed for TO2//modify *(VP_U32)CRM_CSCR &= ~0xe0000000; //set back PRESC = b000 (i.e./1)//end//Changed for T02 } // No Meaning as ipg_clk = ipg_per_clk // Set up PLL and Clock controller module // 127.9999738MHz / 4 = 31.99999346MHz // set PERDIV1 to b0011 i.e. /4 (***no meaning for TO1 as ipg_clk = ipg_per_clk, for TO2 only) *(VP_U32)CRM_PCDR1 |= 0x5; *(VP_U32)CRM_PCDR1 &= 0xffffffc5; } //PLL bypass mode (MPLL = 128MHz) else { // 128MHz/ (1 [PRESC = b00, /1] * 2 [BCLKDIV=b0001, /2] * 2 [IPDIV=b1, /2]) // = ipg_clk = ipg_per_clk (32MHz) // HCLK = 64MHz // FLCK = 128MHz // {Changed for TO2 temp = *(VP_U32)CRM_CSCR; temp |= 0x0000C000; *(VP_U32)CRM_CSCR = temp; //set PRESC = b11 (i.e. /4) will change to /1 later// Changed for TO2 } temp = *(VP_U32)CRM_CSCR; temp |= 0x00000200; *(VP_U32)CRM_CSCR = temp; //set IPDIV = 1 temp = *(VP_U32)CRM_CSCR; temp &= ~0x00003C00; temp |= 0x00000400; *(VP_U32)CRM_CSCR = temp; // set BCLKDIV = 1 (i.e. /2) // { Changed for TO2 *(VP_U32)CRM_CSCR &= ~0xe0000000; //set back PRESC = b00 (i.e./1)// Changed for TO2 } // No Meaning as ipg_clk = ipg_per_clk // Set up PLL and Clock controller module // set PERDIV1 to b0011 i.e. /4 (***no meaning for TO1 as ipg_clk = ipg_per_clk, for TO2 only) *(VP_U32)CRM_PCDR1 |= 0x5; *(VP_U32)CRM_PCDR1 &= 0xFFFFFFC5; } //enable clock for HCLK BROM and UART1 *(VP_U32)CRM_PCCR0 |= 0x10000001; // software reset *(VP_U32)UART1_CR2 = 0x0; //write 1 to RXDMUXSEL = 1 *(VP_U32)UART1_CR3 |= 0x4; // software reset *(VP_U32)UART2_CR2 = 0x0; //write 1 to RXDMUXSEL = 1 *(VP_U32)UART2_CR3 |= 0x4; //================================================================= // Set up GPIO/IOMUX for UART1 *(VP_U32)GPIOE_GIUS &= 0xFFFF0FFF; // clear bit 12-bit 15 of GIUS_E *(VP_U32)GPIOE_GPR &= 0xFFFF0FFF; // clear bit 12-bit 15 of GPR_E //================================================================= *(VP_U32)GPIOE_GIUS &= ~0x00000d8; //port E pin 3,4,6,7 for uart2 *(VP_U32)GPIOE_GPR &= ~0x00000d8; //port E pin 3,4,6,7 for primary function // Configure SPLL to 288MHz and usbdiv=5(/6) if (*(VP_U32)SYS_FMCR & 0xC0000000) { //configure the Clock - usbdiv=5 (/6), clkdiv=0 temp = *(VP_U32)CRM_CSCR; temp &= ~0x1C000000; temp |= 0x14000000; *(VP_U32)CRM_CSCR = temp; //PLL input freq = 32.768kHz //PLL output frequency =288 MHz USBDIV='b101, USBCLK =48M *(VP_U32)CRM_SPCTL0 = 0x272216d;//288Mhz //*(VP_U32)CRM_SPCTL0 = 0x03811C89; //240Mhz //set the SPLL_RESTART bit in CSCR *(VP_U32)CRM_CSCR |= 0x00400000; //wait for the SPLLRESTART bit self clear while (*(VP_U32)CRM_CSCR & 0x00400000); //wait for the SPLL Lock Flag to clear while (*(VP_U32)CRM_SPCTL1 & 0x00008000); //wait for the SPLL Lock Flag to set while (!(*(VP_U32)CRM_SPCTL1 & 0x00008000)); // new PLL setting will take place // connect CLKO to CLK48M #if 0 temp = *(VP_U32)CRM_CCSR; temp &= 0xfffffff4; temp |= 0x00000414; *(VP_U32)CRM_CCSR = temp;#endif } //PLL bypass mode (SPLL = 48MHz) else { //configure the Clock - usbdiv=0 (/1), clkdiv=0 temp = *(VP_U32)CRM_CSCR; temp &= ~0x1C000000; *(VP_U32)CRM_CSCR = temp; }}///Config MX21 Uart1 As 115200-B-N-1void MX21_InitInternalUART(void){ //software reset *(VP_U32)UART1_CR2 = 0x61E6; *(VP_U32)UART1_CR1 = 0x0; *(VP_U32)UART1_CR3 = 0x4; *(VP_U32)UART1_CR4 = 0x8000;// configure appropriate pins for UART1_RX, UART1_TX, UART2_RX and UART2_TX *(VP_U32)UART1_CR1 = 0x0005; // UARTEN = 1,enable the clock //UCR2 = CTSC,TXEN,RXEN=1,reset, ignore IRTS bit, WS = 1 , //8 bit tx and rx,1 stop bit, disable parity *(VP_U32)UART1_CR2 = 0x6026; *(VP_U32)UART1_CR3 = 0x0004; *(VP_U32)UART1_CR4 = 0x8000; //================================================================= // Set up reference freq divide for UART module // MX2 only support 16MHz output // PerCLK1(31.99998691MHz)/UFCR[RFDIV] (2)= 15.99999673MHz *(VP_U32)UART1_FCR = 0x0A01; // CKIH = PerCLK1 set to div by 1 (UART 1) //================================================================= //clear loopback bit *(VP_U32)UART1_TS = 0x0000; //reference frequency is 16MHz //BIR_115200 = 1151 //NUM = 1151+1 DENOM = 9999+1 //thus NUM/DENOM = 0.1152 --> gives baud rate: 115200 // { Changed for TO2 *(VP_U32)UART1_BIR = 837; // configure UBIR// Changed for TO2 } *(VP_U32)UART1_BMR = 9999; // configure UBMR }///@brief Check if rx FIFO Ready///@return @li 0: not ready/// @li not 0: ReadyU8 EUARTdataReady(){ return _reg_USR2 & RDR_MASK; // check RDR bit}///@brief Send Data ///@param data will be sentvoid EUARTputData(U8 data){ while (!(_reg_USR2 & TXFE_MASK)); // wait until TXFE bit set _reg_UTXD = (U16)data; if (data == '\n') // carriage return ? append line-feed { while (!(_reg_USR2 & TXFE_MASK)); // wait until TXFE bit set _reg_UTXD = '\r'; }}///@brief Get Data///@return data recieved by UARTU8 EUARTgetData(){ while (!EUARTdataReady()); // wait until RDR bit set return (U8)_reg_URXD;}///@brief Put data as Hex format///@param data data will be sentvoid EUARTputHex(U8 data){ U8 d; // print first digit d = data >> 4; if (d > 9) d += 55; else d += '0'; EUARTputData(d); // print second digit d = data & 0xF; if (d > 9) d += 55; else d += '0'; EUARTputData(d);}///@brief put string to uart///@param line string will be sent by Uartvoid EUARTputString(U8 *line){ while (*line) { EUARTputData(*(line++)); }}//>>>>>Body⌨️ 快捷键说明
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