📄 usbotg_internal.h
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#define INT_TRUE_REG_SET_ADD OTG_I2C_BASE+0x0e
#define INT_TRUE_REG_CLR_ADD OTG_I2C_BASE+0x0f
#define OTG_CTRL_REG2_SET_ADD OTG_I2C_BASE+0x10
#define OTG_CTRL_REG2_CLR_ADD OTG_I2C_BASE+0x11
#define MODE_REG2_SET_ADD OTG_I2C_BASE+0x12
#define MODE_REG2_CLR_ADD OTG_I2C_BASE+0x13
#define BCD_DEV_REG0_ADD OTG_I2C_BASE+0x14
#define BCD_DEV_REG1_ADD OTG_I2C_BASE+0x15
#define OTG_XCVR_DEVAD_ADD OTG_I2C_BASE+0x18
#define SEQ_OP_REG_ADD OTG_I2C_BASE+0x19
#define SEQ_RD_STARTAD_ADD OTG_I2C_BASE+0x1a
#define I2C_OP_CTRL_REG_ADD OTG_I2C_BASE+0x1b
#define SCLK_TO_SCL_HPER_ADD OTG_I2C_BASE+0x1e
#define I2C_MASTER_INT_REG_ADD OTG_I2C_BASE+0x1f
//
// ;---------------------------------------;
// ; Clock & Reset (CRM) ;
// ; &1002_7000 to $1002_7020 ;
// ;---------------------------------------;
#define CRM_BASE_ADDR 0x10027000
#define CRM_CSCR CRM_BASE_ADDR // ; Clock Source Control Reg
#define CRM_MPCTL0 (CRM_BASE_ADDR+0x04) // ; MCU PLL Control Reg
#define CRM_MPCTL1 (CRM_BASE_ADDR+0x08) // ; MCU PLL & System Clk Ctl Reg
#define CRM_SPCTL0 (CRM_BASE_ADDR+0x0C) // ; USB PLL Control Reg 0
#define CRM_SPCTL1 (CRM_BASE_ADDR+0x10) // ; USB PLL Control Reg 1
#define CRM_OSC26MCTL (CRM_BASE_ADDR+0x14) // ; Oscillator 26M Register
#define CRM_PCDR (CRM_BASE_ADDR+0x18) // ; Perpheral Clock Divider Reg
#define CRM_PCCR0 (CRM_BASE_ADDR+0x1C) // ; Perpheral Clock Control Reg0
#define CRM_PCCR1 (CRM_BASE_ADDR+0x20) // ; Perpheral Clock Control Reg1
//;#########################################
//;# MAX #
//;# $1003_F000 to $1003_FFFF #
//;#########################################
#define MAX_BASE_ADDR 0x1003F000
#define MAX_SLV0_BASE (MAX_BASE_ADDR+0x000) // base location for slave 0
#define MAX_SLV1_BASE (MAX_BASE_ADDR+0x100) // base location for slave 1
#define MAX_SLV2_BASE (MAX_BASE_ADDR+0x200) // base location for slave 2
#define MAX_SLV3_BASE (MAX_BASE_ADDR+0x300) // base location for slave 3
#define MAX_SLV0_MPR0 (MAX_SLV0_BASE+0x00) // 32bit max slv0 master priority reg
#define MAX_SLV0_AMPR0 (MAX_SLV0_BASE+0x04) // 32bit max slv0 alt priority reg
#define MAX_SLV0_SGPCR0 (MAX_SLV0_BASE+0x10) // 32bit max slv0 general ctrl reg
#define MAX_SLV0_ASGPCR0 (MAX_SLV0_BASE+0x14) // 32bit max slv0 alt generl ctrl reg
#define MAX_SLV1_MPR1 (MAX_SLV1_BASE+0x00) // 32bit max slv1 master priority reg
#define MAX_SLV1_AMPR1 (MAX_SLV1_BASE+0x04) // 32bit max slv1 alt priority reg
#define MAX_SLV1_SGPCR1 (MAX_SLV1_BASE+0x10) // 32bit max slv1 general ctrl reg
#define MAX_SLV1_ASGPCR1 (MAX_SLV1_BASE+0x14) // 32bit max slv1 alt generl ctrl reg
#define MAX_SLV2_MPR2 (MAX_SLV2_BASE+0x00) // 32bit max slv2 master priority reg
#define MAX_SLV2_AMPR2 (MAX_SLV2_BASE+0x04) // 32bit max slv2 alt priority reg
#define MAX_SLV2_SGPCR2 (MAX_SLV2_BASE+0x10) // 32bit max slv2 general ctrl reg
#define MAX_SLV2_ASGPCR2 (MAX_SLV2_BASE+0x14) // 32bit max slv2 alt generl ctrl reg
#define MAX_SLV3_MPR3 (MAX_SLV3_BASE+0x00) // 32bit max slv3 master priority reg
#define MAX_SLV3_AMPR3 (MAX_SLV3_BASE+0x04) // 32bit max slv3 alt priority reg
#define MAX_SLV3_SGPCR3 (MAX_SLV3_BASE+0x10) // 32bit max slv3 general ctrl reg
#define MAX_SLV3_ASGPCR3 (MAX_SLV3_BASE+0x14) // 32bit max slv3 alt generl ctrl reg
#define MAX_MST0_MGPCR0 (MAX_BASE_ADDR+0x800) // 32bit max mst0 general ctrl reg
#define MAX_MST1_MGPCR1 (MAX_BASE_ADDR+0x900) // 32bit max mst1 general ctrl reg
#define MAX_MST2_MGPCR2 (MAX_BASE_ADDR+0xA00) // 32bit max mst2 general ctrl reg
#define MAX_MST3_MGPCR3 (MAX_BASE_ADDR+0xB00) // 32bit max mst3 general ctrl reg
#define MAX_MST4_MGPCR4 (MAX_BASE_ADDR+0xC00) // 32bit max mst4 general ctrl reg
#define MAX_MST5_MGPCR5 (MAX_BASE_ADDR+0xD00) // 32bit max mst5 general ctrl reg
//
// ;---------------------------------------;
// ; WEIM ;
// ; $DF00_1000 to $DF00_1030 ;
// ;---------------------------------------;
#define WEIM_BASE_ADDR 0xDF001000
#define WEIM_CS0U EIM_BASE_ADDR
#define WEIM_CS0L (EIM_BASE_ADDR+0x04)
#define WEIM_CS1U (EIM_BASE_ADDR+0x08)
#define WEIM_CS1L (EIM_BASE_ADDR+0x0C)
#define WEIM_CS2U (EIM_BASE_ADDR+0x10)
#define WEIM_CS2L (EIM_BASE_ADDR+0x14)
#define WEIM_CS3U (EIM_BASE_ADDR+0x18)
#define WEIM_CS3L (EIM_BASE_ADDR+0x1C)
#define WEIM_CS4U (EIM_BASE_ADDR+0x20)
#define WEIM_CS4L (EIM_BASE_ADDR+0x24)
#define WEIM_CS5U (EIM_BASE_ADDR+0x28)
#define WEIM_CS5L (EIM_BASE_ADDR+0x2C)
#define WEIM_EIM (EIM_BASE_ADDR+0x30)
#ifdef FPGA
#define EUART_BASE_ADDR 0x17000000
#define EUART_DR (EUART_BASE_ADDR+0x0)
#define EUART_RSR (EUART_BASE_ADDR+0x4)
#define EUART_ECR (EUART_BASE_ADDR+0x4)
#define EUART_LCRH (EUART_BASE_ADDR+0x8)
#define EUART_LCRM (EUART_BASE_ADDR+0xC)
#define EUART_LCRL (EUART_BASE_ADDR+0x10)
#define EUART_CR (EUART_BASE_ADDR+0x14)
#define EUART_FR (EUART_BASE_ADDR+0x18)
#define EUART_IIR (EUART_BASE_ADDR+0x1C)
#define EUARTI_ICR (EUART_BASE_ADDR+0x1C)
#define LM_AIPI 0xC0000000
#define LM_SW 0xC0001014
//#define LM_SW 0xC0000014
#define LED_BASE 0x1A000000
#define LED_ALPHA (LED_BASE+0x0)
#define LED_LIGHTS (LED_BASE+0x4)
#define LED_SWITCHES (LED_BASE+0x8)
#endif
/***************** End of Tahiti definition **************************/
/***************** UsbOtg definition **************************/
//EPConfig for EP0 OUT
#define EP0OutDW0 0x00080000 // configure EP0 for CTRL setup
#define EP0OutDW1 0x00000000 // XBuff and YBuff are 0
//#define EP0OutDW2 // Reserved
#define EP0OutDW3_8Byte 0x00E00008 // TotalByteCnt = 8 bytes
#define EP0OutDW3_Empty 0x00E00000 // TotalByteCnt = 0 Bytes
//EPConfig for EP0 IN (Empty Packet)
#define EP0InDW0 0x00080000 // configure EP0 for CTRL setup
#define EP0InDW1 0x00000020 // XBuff and YBuff are 0
//#define EP0InDW2 // Reserved
#define EP0InDW3_EMPTY 0x00E00000 // TotalByteCnt = 0 bytes
#define EP1OutDataMemoryOffset 0x20
#define EP1InDataMemoryOffset 0x30
#define CommandLength 0x10
#define AckCommandLength 0x4
/*otg control1
*/
#define I2C_MASK_DP_PULLUP 0x01
#define I2C_MASK_DM_PULLUP 0x02
#define I2C_MASK_DP_PULLDOWN 0x04
#define I2C_MASK_DM_PULLDOWN 0x08
#define EP_OUT_DIR 0
#define EP_IN_DIR 1
#define EP_NO_STALL 0
#define EP_STALL 1
#define EP_NO_SETUP 0
#define EP_SETUP 1
#define CTL_TYPE 0x0
#define BLK_TYPE 0x2
U32 EP_table_entry[32];
U32 EP_totalbyte[32];
U32 EP_active; /*initialise all eps to be inactive */
//U32 dgcEpNextBufToService; /*initialise to X buffers for all 32 entries.*/
U8 dgcEpFillDrainN;
U8 dgcEpXStatus;
U8 dgcEpYStatus;
U32 dgcEpStartAddress;
U32 EP_DMA_smsa[32];
U8 r_i2cDevAddr; /* 1 byte */
U8 r_i2cRdData; /* 1 byte */
U32 r_i2cHwSw;
U32 r_i2cStartAddr;
U8 rExpRegAddr; /* for saving the current start address for auto-checking */
/*============Function related tasks==========*/
void EPConfig(U32 ep, U32 dir, U32 stall, U32 setup, U32 MPS, U32 format, U32 xbsa, U32 ybsa, U32 Bufsize, U32 Tbyte);
void WriteEPToggleBit(U8 ep, U8 dir, U8 toggle_val);
void Enable_EP(U8 ep_num);
void Disable_EP(U8 ep_num);
U8 check_ep_ready(U8 qEpNumberDirection);
void toggle_ready_ep(U8 ep_num, U8 ready);
void Ready_EP_IN(U8 ep);
void Ready_EP_OUT(U8 ep);
void unready_ep_in(U8 ep);
void unready_ep_out(U8 ep);
void Disable_EP_OUT(U8 ep);
void Disable_EP_IN(U8 ep);
void WaitOnEPDone_OUT(U8 ep);
void Clear_active_ep(U8 ep_num);
/*=====Common tasks ======*/
void SetOtgPort_FunctionMode(void);
void OtgPort_ExtPullUpDisabled(void);
void OtgPort_PullUpEnabled(void);
/*=====i2c tasks ======= */
void i2cDpPullUp(void);
/* ------ newly added routine ------ */
void i2cSetSeqOpReg(U8 qWrData);
void i2cCheckBusy(void);
void i2cSetSeqRdStartAd(U8 qWrData);
void i2cSingleRegWrite(U32 qRegAddr, U8 qWrData);
void ToggleNextBufferToService(U8 mask);
void ClearXYBufferInt(void);
void EP0OutForRequest(void);
/***************** End of UsbOtg definition **************************/
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