usbotg_internal.h

mx21的NAND Flash Bootloader源代码

			
#define OTG_ETD_BASE	       	(OTG_BASE_ADDR+0x200)		//  base location for etd memory
#define OTG_EP_BASE	       	(OTG_BASE_ADDR+0x400)		//  base location for ep memory
#define OTG_SYS_BASE	       	(OTG_BASE_ADDR+0x600)		//  base location for system
#define OTG_DATA_BASE	       	(OTG_BASE_ADDR+0x1000)	//  base location for data memory

#define OTG_SYS_CTRL	       		(OTG_SYS_BASE+0x000)	//  base location for system
			
#define OTG_CORE_HWMODE	       		(OTG_CORE_BASE+0x00)     //  32bit core hardware mode reg
#define OTG_CORE_CINT_STAT	       	(OTG_CORE_BASE+0x04)     //  32bit core int status reg
#define OTG_CORE_CINT_STEN	       	(OTG_CORE_BASE+0x08)     //  32bit core int enable reg
#define OTG_CORE_CLK_CTRL	       	(OTG_CORE_BASE+0x0C)     //  32bit core clock control reg
#define OTG_CORE_RST_CTRL	       	(OTG_CORE_BASE+0x10)     //  32bit core reset control reg
#define OTG_CORE_FRM_INTVL	       	(OTG_CORE_BASE+0x14)     //  32bit core frame interval reg
#define OTG_CORE_FRM_REMAIN	       	(OTG_CORE_BASE+0x18)     //  32bit core frame remaining reg
#define OTG_CORE_HNP_CSTAT	       	(OTG_CORE_BASE+0x1C)     //  32bit core HNP current state reg
#define OTG_CORE_HNP_TIMER1	       	(OTG_CORE_BASE+0x20)     //  32bit core HNP timer 1 reg
#define OTG_CORE_HNP_TIMER2	       	(OTG_CORE_BASE+0x24)     //  32bit core HNP timer 2 reg
#define OTG_CORE_HNP_T3PCR	       	(OTG_CORE_BASE+0x28)     //  32bit core HNP timer 3 pulse ctrl
#define OTG_CORE_HINT_STAT	       	(OTG_CORE_BASE+0x2C)     //  32bit core HNP int status reg
#define OTG_CORE_HINT_STEN	       	(OTG_CORE_BASE+0x30)     //  32bit core HNP int enable reg
			
#define OTG_FUNC_CND_STAT	       	(OTG_FUNC_BASE+0x00)     //  32bit func command status reg
#define OTG_FUNC_DEV_ADDR	       	(OTG_FUNC_BASE+0x04)     //  32bit func device address reg
#define OTG_FUNC_SINT_STAT	       	(OTG_FUNC_BASE+0x08)     //  32bit func system int status reg
#define OTG_FUNC_SINT_STEN	       	(OTG_FUNC_BASE+0x0C)     //  32bit func system int enable reg
#define OTG_FUNC_XINT_STAT	       	(OTG_FUNC_BASE+0x10)     //  32bit func X buf int status reg
#define OTG_FUNC_YINT_STAT	       	(OTG_FUNC_BASE+0x14)     //  32bit func Y buf int status reg
#define OTG_FUNC_XYINT_STEN	       	(OTG_FUNC_BASE+0x18)     //  32bit func XY buf int enable reg
#define OTG_FUNC_XFILL_STAT	       	(OTG_FUNC_BASE+0x1C)     //  32bit func X filled status reg
#define OTG_FUNC_YFILL_STAT	       	(OTG_FUNC_BASE+0x20)     //  32bit func Y filled status reg
#define OTG_FUNC_EP_EN	       		(OTG_FUNC_BASE+0x24)     //  32bit func endpoints enable reg
#define OTG_FUNC_EP_RDY	       		(OTG_FUNC_BASE+0x28)     //  32bit func endpoints ready reg
#define OTG_FUNC_IINT	       		(OTG_FUNC_BASE+0x2C)     //  32bit func immediate interrupt reg
#define OTG_FUNC_EP_DSTAT	       	(OTG_FUNC_BASE+0x30)     //  32bit func endpoints done status
#define OTG_FUNC_EP_DEN	       		(OTG_FUNC_BASE+0x34)     //  32bit func endpoints done enable
#define OTG_FUNC_EP_TOGGLE	       	(OTG_FUNC_BASE+0x38)     //  32bit func endpoints toggle bits
#define OTG_FUNC_FRM_NUM	       	(OTG_FUNC_BASE+0x3C)     //  32bit func frame number reg
			
#define OTG_HOST_CTRL	       		(OTG_HOST_BASE+0x00)     //  32bit host controller config reg
#define OTG_HOST_SINT_STAT	       	(OTG_HOST_BASE+0x08)     //  32bit host system int status reg
#define OTG_HOST_SINT_STEN	       	(OTG_HOST_BASE+0x0C)     //  32bit host system int enable reg
#define OTG_HOST_XINT_STAT	       	(OTG_HOST_BASE+0x18)     //  32bit host X buf int status reg
#define OTG_HOST_YINT_STAT	       	(OTG_HOST_BASE+0x1C)     //  32bit host Y buf int status reg
#define OTG_HOST_XYINT_STEN	       	(OTG_HOST_BASE+0x20)     //  32bit host XY buf int enable reg
#define OTG_HOST_XFILL_STAT	       	(OTG_HOST_BASE+0x28)     //  32bit host X filled status reg
#define OTG_HOST_YFILL_STAT	       	(OTG_HOST_BASE+0x2C)     //  32bit host Y filled status reg
#define OTG_HOST_ETD_EN	       		(OTG_HOST_BASE+0x40)     //  32bit host ETD enables reg
#define OTG_HOST_DIR_ROUTE	       	(OTG_HOST_BASE+0x48)     //  32bit host direct routing reg
#define OTG_HOST_IINT	       		(OTG_HOST_BASE+0x4C)     //  32bit host immediate interrupt reg
#define OTG_HOST_EP_DSTAT	       	(OTG_HOST_BASE+0x50)     //  32bit host endpoints done status
#define OTG_HOST_ETD_DONE	       	(OTG_HOST_BASE+0x54)     //  32bit host ETD done reg
#define OTG_HOST_FRM_NUM	       	(OTG_HOST_BASE+0x60)     //  32bit host frame number reg
#define OTG_HOST_LSP_THRESH	       	(OTG_HOST_BASE+0x64)     //  32bit host low speed threshold reg
#define OTG_HOST_HUB_DESCA	       	(OTG_HOST_BASE+0x68)     //  32bit host root hub descriptor A
#define OTG_HOST_HUB_DESCB	       	(OTG_HOST_BASE+0x6C)     //  32bit host root hub descriptor B
#define OTG_HOST_HUB_STAT	       	(OTG_HOST_BASE+0x70)     //  32bit host root hub status reg
#define OTG_HOST_PORT1_STAT	       	(OTG_HOST_BASE+0x74)     //  32bit host port 1 status bits
#define OTG_HOST_PORT2_STAT	       	(OTG_HOST_BASE+0x78)     //  32bit host port 2 status bits
#define OTG_HOST_PORT3_STAT	       	(OTG_HOST_BASE+0x7c)     //  32bit host port 3 status bits
			
#define OTG_DMA_REV_NUM	       		(OTG_DMA_BASE+0x000)     //  32bit dma revision number reg
#define OTG_DMA_DINT_STAT	       	(OTG_DMA_BASE+0x004)     //  32bit dma int status reg
#define OTG_DMA_DINT_STEN	       	(OTG_DMA_BASE+0x008)     //  32bit dma int enable reg
#define OTG_DMA_ETD_ERR	       		(OTG_DMA_BASE+0x00C)     //  32bit dma ETD error status reg
#define OTG_DMA_EP_ERR	       		(OTG_DMA_BASE+0x010)     //  32bit dma EP error status reg
#define OTG_DMA_ETD_EN	       		(OTG_DMA_BASE+0x020)     //  32bit dma ETD DMA enable reg
#define OTG_DMA_EP_EN	       		(OTG_DMA_BASE+0x024)     //  32bit dma EP DMA enable reg
#define OTG_DMA_ETD_ENXREQ	       	(OTG_DMA_BASE+0x028)     //  32bit dma ETD DMA enable Xtrig req
#define OTG_DMA_EP_ENXREQ	       	(OTG_DMA_BASE+0x02C)     //  32bit dma EP DMA enable Ytrig req
#define OTG_DMA_ETD_ENXYREQ	       	(OTG_DMA_BASE+0x030)     //  32bit dma ETD DMA enble XYtrig req
#define OTG_DMA_EP_ENXYREQ	       	(OTG_DMA_BASE+0x034)     //  32bit dma EP DMA enable XYtrig req
#define OTG_DMA_ETD_BURST4	       	(OTG_DMA_BASE+0x038)     //  32bit dma ETD DMA enble burst4 reg
#define OTG_DMA_EP_BURST4	       	(OTG_DMA_BASE+0x03C)     //  32bit dma EP DMA enable burst4 reg
#define OTG_DMA_MISC_CTRL	       	(OTG_DMA_BASE+0x040)     //  32bit dma EP misc control reg
#define OTG_DMA_ETD_CH_CLR	       	(OTG_DMA_BASE+0x044)     //  32bit dma ETD clear channel reg
#define OTG_DMA_EP_CH_CLR	       	(OTG_DMA_BASE+0x048)     //  32bit dma EP clear channel reg
			
#define OTG_DMA_ETD0_MSA	       	(OTG_DMA_BASE+0x100)     //  32bit dma ETD0 mem start addr reg
#define OTG_DMA_ETD1_MSA	       	(OTG_DMA_BASE+0x104)     //  32bit dma ETD1 mem start addr reg
#define OTG_DMA_ETD2_MSA	       	(OTG_DMA_BASE+0x108)     //  32bit dma ETD2 mem start addr reg
#define OTG_DMA_ETD3_MSA	       	(OTG_DMA_BASE+0x10C)     //  32bit dma ETD3 mem start addr reg
#define OTG_DMA_ETD4_MSA	       	(OTG_DMA_BASE+0x110)     //  32bit dma ETD4 mem start addr reg
#define OTG_DMA_ETD5_MSA	       	(OTG_DMA_BASE+0x114)     //  32bit dma ETD5 mem start addr reg
#define OTG_DMA_ETD6_MSA	       	(OTG_DMA_BASE+0x118)     //  32bit dma ETD6 mem start addr reg
#define OTG_DMA_ETD7_MSA	       	(OTG_DMA_BASE+0x11C)     //  32bit dma ETD7 mem start addr reg
#define OTG_DMA_ETD8_MSA	       	(OTG_DMA_BASE+0x120)     //  32bit dma ETD8 mem start addr reg
#define OTG_DMA_ETD9_MSA	       	(OTG_DMA_BASE+0x124)     //  32bit dma ETD9 mem start addr reg
#define OTG_DMA_ETD10_MSA	       	(OTG_DMA_BASE+0x128)     //  32bit dma ETD10 mem start addr reg
#define OTG_DMA_ETD11_MSA	       	(OTG_DMA_BASE+0x12C)     //  32bit dma ETD11 mem start addr reg
#define OTG_DMA_ETD12_MSA	       	(OTG_DMA_BASE+0x130)     //  32bit dma ETD12 mem start addr reg
#define OTG_DMA_ETD13_MSA	       	(OTG_DMA_BASE+0x134)     //  32bit dma ETD13 mem start addr reg
#define OTG_DMA_ETD14_MSA	       	(OTG_DMA_BASE+0x138)     //  32bit dma ETD14 mem start addr reg
#define OTG_DMA_ETD15_MSA	       	(OTG_DMA_BASE+0x13C)     //  32bit dma ETD15 mem start addr reg
#define OTG_DMA_ETD16_MSA	       	(OTG_DMA_BASE+0x140)     //  32bit dma ETD16 mem start addr reg
#define OTG_DMA_ETD17_MSA	       	(OTG_DMA_BASE+0x144)     //  32bit dma ETD17 mem start addr reg
#define OTG_DMA_ETD18_MSA	       	(OTG_DMA_BASE+0x148)     //  32bit dma ETD18 mem start addr reg
#define OTG_DMA_ETD19_MSA	       	(OTG_DMA_BASE+0x14C)     //  32bit dma ETD19 mem start addr reg
#define OTG_DMA_ETD20_MSA	       	(OTG_DMA_BASE+0x150)     //  32bit dma ETD20 mem start addr reg
#define OTG_DMA_ETD21_MSA	       	(OTG_DMA_BASE+0x154)     //  32bit dma ETD21 mem start addr reg
#define OTG_DMA_ETD22_MSA	       	(OTG_DMA_BASE+0x158)     //  32bit dma ETD22 mem start addr reg
#define OTG_DMA_ETD23_MSA	       	(OTG_DMA_BASE+0x15C)     //  32bit dma ETD23 mem start addr reg
#define OTG_DMA_ETD24_MSA	       	(OTG_DMA_BASE+0x160)     //  32bit dma ETD24 mem start addr reg
#define OTG_DMA_ETD25_MSA	       	(OTG_DMA_BASE+0x164)     //  32bit dma ETD25 mem start addr reg
#define OTG_DMA_ETD26_MSA	       	(OTG_DMA_BASE+0x168)     //  32bit dma ETD26 mem start addr reg
#define OTG_DMA_ETD27_MSA	       	(OTG_DMA_BASE+0x16C)     //  32bit dma ETD27 mem start addr reg
#define OTG_DMA_ETD28_MSA	       	(OTG_DMA_BASE+0x170)     //  32bit dma ETD28 mem start addr reg
#define OTG_DMA_ETD29_MSA	       	(OTG_DMA_BASE+0x174)     //  32bit dma ETD29 mem start addr reg
#define OTG_DMA_ETD30_MSA	       	(OTG_DMA_BASE+0x178)     //  32bit dma ETD30 mem start addr reg
#define OTG_DMA_ETD31_MSA	       	(OTG_DMA_BASE+0x17C)     //  32bit dma ETD31 mem start addr reg
			
#define OTG_DMA_EP0_O_MSA	       	(OTG_DMA_BASE+0x180)     //  32bit dma EP0 o/p mem start addr
#define OTG_DMA_EP0_I_MSA	       	(OTG_DMA_BASE+0x184)     //  32bit dma EP0 i/p mem start addr
#define OTG_DMA_EP1_O_MSA	       	(OTG_DMA_BASE+0x188)     //  32bit dma EP1 o/p mem start addr
#define OTG_DMA_EP1_I_MSA	       	(OTG_DMA_BASE+0x18C)     //  32bit dma EP1 i/p mem start addr
#define OTG_DMA_EP2_O_MSA	       	(OTG_DMA_BASE+0x190)     //  32bit dma EP2 o/p mem start addr
#define OTG_DMA_EP2_I_MSA	       	(OTG_DMA_BASE+0x194)     //  32bit dma EP2 i/p mem start addr
#define OTG_DMA_EP3_O_MSA	       	(OTG_DMA_BASE+0x198)     //  32bit dma EP3 o/p mem start addr
#define OTG_DMA_EP3_I_MSA	       	(OTG_DMA_BASE+0x19C)     //  32bit dma EP3 i/p mem start addr
#define OTG_DMA_EP4_O_MSA	       	(OTG_DMA_BASE+0x1A0)     //  32bit dma EP4 o/p mem start addr
#define OTG_DMA_EP4_I_MSA	       	(OTG_DMA_BASE+0x1A4)     //  32bit dma EP4 i/p mem start addr
#define OTG_DMA_EP5_O_MSA	       	(OTG_DMA_BASE+0x1A8)     //  32bit dma EP5 o/p mem start addr
#define OTG_DMA_EP5_I_MSA	       	(OTG_DMA_BASE+0x1AC)     //  32bit dma EP5 i/p mem start addr
#define OTG_DMA_EP6_O_MSA	       	(OTG_DMA_BASE+0x1B0)     //  32bit dma EP6 o/p mem start addr
#define OTG_DMA_EP6_I_MSA	       	(OTG_DMA_BASE+0x1B4)     //  32bit dma EP6 i/p mem start addr
#define OTG_DMA_EP7_O_MSA	       	(OTG_DMA_BASE+0x1B8)     //  32bit dma EP7 o/p mem start addr
#define OTG_DMA_EP7_I_MSA	       	(OTG_DMA_BASE+0x1BC)     //  32bit dma EP7 i/p mem start addr
#define OTG_DMA_EP8_O_MSA	       	(OTG_DMA_BASE+0x1C0)     //  32bit dma EP8 o/p mem start addr
#define OTG_DMA_EP8_I_MSA	       	(OTG_DMA_BASE+0x1C4)     //  32bit dma EP8 i/p mem start addr
#define OTG_DMA_EP9_O_MSA	       	(OTG_DMA_BASE+0x1C8)     //  32bit dma EP9 o/p mem start addr
#define OTG_DMA_EP9_I_MSA	       	(OTG_DMA_BASE+0x1CC)     //  32bit dma EP9 i/p mem start addr
#define OTG_DMA_EP10_O_MSA	       	(OTG_DMA_BASE+0x1D0)     //  32bit dma EP10 o/p mem start addr
#define OTG_DMA_EP10_I_MSA	       	(OTG_DMA_BASE+0x1D4)     //  32bit dma EP10 i/p mem start addr
#define OTG_DMA_EP11_O_MSA	       	(OTG_DMA_BASE+0x1D8)     //  32bit dma EP11 o/p mem start addr
#define OTG_DMA_EP11_I_MSA	       	(OTG_DMA_BASE+0x1DC)     //  32bit dma EP11 i/p mem start addr
#define OTG_DMA_EP12_O_MSA	       	(OTG_DMA_BASE+0x1E0)     //  32bit dma EP12 o/p mem start addr
#define OTG_DMA_EP12_I_MSA	       	(OTG_DMA_BASE+0x1E4)     //  32bit dma EP12 i/p mem start addr
#define OTG_DMA_EP13_O_MSA	       	(OTG_DMA_BASE+0x1E8)     //  32bit dma EP13 o/p mem start addr
#define OTG_DMA_EP13_I_MSA	       	(OTG_DMA_BASE+0x1EC)     //  32bit dma EP13 i/p mem start addr
#define OTG_DMA_EP14_O_MSA	       	(OTG_DMA_BASE+0x1F0)     //  32bit dma EP14 o/p mem start addr
#define OTG_DMA_EP14_I_MSA	       	(OTG_DMA_BASE+0x1F4)     //  32bit dma EP14 i/p mem start addr
#define OTG_DMA_EP15_O_MSA	       	(OTG_DMA_BASE+0x1F8)     //  32bit dma EP15 o/p mem start addr
#define OTG_DMA_EP15_I_MSA	       	(OTG_DMA_BASE+0x1FC)     //  32bit dma EP15 i/p mem start addr
			
#define OTG_DMA_ETD0_BPTR	       	(OTG_DMA_BASE+0x200)     //  32bit dma ETD0 buf tx pointer reg
#define OTG_DMA_ETD1_BPTR	       	(OTG_DMA_BASE+0x204)     //  32bit dma ETD1 buf tx pointer reg
#define OTG_DMA_ETD2_BPTR	       	(OTG_DMA_BASE+0x208)     //  32bit dma ETD2 buf tx pointer reg
#define OTG_DMA_ETD3_BPTR	       	(OTG_DMA_BASE+0x20C)     //  32bit dma ETD3 buf tx pointer reg
#define OTG_DMA_ETD4_BPTR	       	(OTG_DMA_BASE+0x210)     //  32bit dma ETD4 buf tx pointer reg
#define OTG_DMA_ETD5_BPTR	       	(OTG_DMA_BASE+0x214)     //  32bit dma ETD5 buf tx pointer reg
#define OTG_DMA_ETD6_BPTR	       	(OTG_DMA_BASE+0x218)     //  32bit dma ETD6 buf tx pointer reg
#define OTG_DMA_ETD7_BPTR	       	(OTG_DMA_BASE+0x21C)     //  32bit dma ETD7 buf tx pointer reg
#define OTG_DMA_ETD8_BPTR	       	(OTG_DMA_BASE+0x220)     //  32bit dma ETD8 buf tx pointer reg
#define OTG_DMA_ETD9_BPTR	       	(OTG_DMA_BASE+0x224)     //  32bit dma ETD9 buf tx pointer reg
#define OTG_DMA_ETD10_BPTR	       	(OTG_DMA_BASE+0x228)     //  32bit dma ETD10 buf tx pointer reg
#define OTG_DMA_ETD11_BPTR	       	(OTG_DMA_BASE+0x22C)     //  32bit dma ETD11 buf tx pointer reg
#define OTG_DMA_ETD12_BPTR	       	(OTG_DMA_BASE+0x230)     //  32bit dma ETD12 buf tx pointer reg
#define OTG_DMA_ETD13_BPTR	       	(OTG_DMA_BASE+0x234)     //  32bit dma ETD13 buf tx pointer reg
#define OTG_DMA_ETD14_BPTR	       	(OTG_DMA_BASE+0x238)     //  32bit dma ETD14 buf tx pointer reg
#define OTG_DMA_ETD15_BPTR	       	(OTG_DMA_BASE+0x23C)     //  32bit dma ETD15 buf tx pointer reg
#define OTG_DMA_ETD16_BPTR	       	(OTG_DMA_BASE+0x240)     //  32bit dma ETD16 buf tx pointer reg
#define OTG_DMA_ETD17_BPTR	       	(OTG_DMA_BASE+0x244)     //  32bit dma ETD17 buf tx pointer reg
#define OTG_DMA_ETD18_BPTR	       	(OTG_DMA_BASE+0x248)     //  32bit dma ETD18 buf tx pointer reg
#define OTG_DMA_ETD19_BPTR	       	(OTG_DMA_BASE+0x24C)     //  32bit dma ETD19 buf tx pointer reg
#define OTG_DMA_ETD20_BPTR	       	(OTG_DMA_BASE+0x250)     //  32bit dma ETD20 buf tx pointer reg
#define OTG_DMA_ETD21_BPTR	       	(OTG_DMA_BASE+0x254)     //  32bit dma ETD21 buf tx pointer reg
#define OTG_DMA_ETD22_BPTR	       	(OTG_DMA_BASE+0x258)     //  32bit dma ETD22 buf tx pointer reg
#define OTG_DMA_ETD23_BPTR	       	(OTG_DMA_BASE+0x25C)     //  32bit dma ETD23 buf tx pointer reg
#define OTG_DMA_ETD24_BPTR	       	(OTG_DMA_BASE+0x260)     //  32bit dma ETD24 buf tx pointer reg
#define OTG_DMA_ETD25_BPTR	       	(OTG_DMA_BASE+0x264)     //  32bit dma ETD25 buf tx pointer reg
#define OTG_DMA_ETD26_BPTR	       	(OTG_DMA_BASE+0x268)     //  32bit dma ETD26 buf tx pointer reg
#define OTG_DMA_ETD27_BPTR	       	(OTG_DMA_BASE+0x26C)     //  32bit dma ETD27 buf tx pointer reg
#define OTG_DMA_ETD28_BPTR	       	(OTG_DMA_BASE+0x270)     //  32bit dma ETD28 buf tx pointer reg
#define OTG_DMA_ETD29_BPTR	       	(OTG_DMA_BASE+0x274)     //  32bit dma ETD29 buf tx pointer reg
#define OTG_DMA_ETD30_BPTR	       	(OTG_DMA_BASE+0x278)     //  32bit dma ETD30 buf tx pointer reg
#define OTG_DMA_ETD31_BPTR	       	(OTG_DMA_BASE+0x27C)     //  32bit dma ETD31 buf tx pointer reg
			
#define OTG_DMA_EP0_O_BPTR	       	(OTG_DMA_BASE+0x280)     //  32bit dma EP0 o/p buf tx pointer
#define OTG_DMA_EP0_I_BPTR	       	(OTG_DMA_BASE+0x284)     //  32bit dma EP0 i/p buf tx pointer
#define OTG_DMA_EP1_O_BPTR	       	(OTG_DMA_BASE+0x288)     //  32bit dma EP1 o/p buf tx pointer
#define OTG_DMA_EP1_I_BPTR	       	(OTG_DMA_BASE+0x28C)     //  32bit dma EP1 i/p buf tx pointer
#define OTG_DMA_EP2_O_BPTR	       	(OTG_DMA_BASE+0x290)     //  32bit dma EP2 o/p buf tx pointer
#define OTG_DMA_EP2_I_BPTR	       	(OTG_DMA_BASE+0x294)     //  32bit dma EP2 i/p buf tx pointer
#define OTG_DMA_EP3_O_BPTR	       	(OTG_DMA_BASE+0x298)     //  32bit dma EP3 o/p buf tx pointer
#define OTG_DMA_EP3_I_BPTR	       	(OTG_DMA_BASE+0x29C)     //  32bit dma EP3 i/p buf tx pointer
#define OTG_DMA_EP4_O_BPTR	       	(OTG_DMA_BASE+0x2A0)     //  32bit dma EP4 o/p buf tx pointer
#define OTG_DMA_EP4_I_BPTR	       	(OTG_DMA_BASE+0x2A4)     //  32bit dma EP4 i/p buf tx pointer
#define OTG_DMA_EP5_O_BPTR	       	(OTG_DMA_BASE+0x2A8)     //  32bit dma EP5 o/p buf tx pointer
#define OTG_DMA_EP5_I_BPTR	       	(OTG_DMA_BASE+0x2AC)     //  32bit dma EP5 i/p buf tx pointer
#define OTG_DMA_EP6_O_BPTR	       	(OTG_DMA_BASE+0x2B0)     //  32bit dma EP6 o/p buf tx pointer
#define OTG_DMA_EP6_I_BPTR	       	(OTG_DMA_BASE+0x2B4)     //  32bit dma EP6 i/p buf tx pointer
#define OTG_DMA_EP7_O_BPTR	       	(OTG_DMA_BASE+0x2B8)     //  32bit dma EP7 o/p buf tx pointer
#define OTG_DMA_EP7_I_BPTR	       	(OTG_DMA_BASE+0x2BC)     //  32bit dma EP7 i/p buf tx pointer
#define OTG_DMA_EP8_O_BPTR	       	(OTG_DMA_BASE+0x2C0)     //  32bit dma EP8 o/p buf tx pointer
#define OTG_DMA_EP8_I_BPTR	       	(OTG_DMA_BASE+0x2C4)     //  32bit dma EP8 i/p buf tx pointer
#define OTG_DMA_EP9_O_BPTR	       	(OTG_DMA_BASE+0x2C8)     //  32bit dma EP9 o/p buf tx pointer
#define OTG_DMA_EP9_I_BPTR	       	(OTG_DMA_BASE+0x2CC)     //  32bit dma EP9 i/p buf tx pointer
#define OTG_DMA_EP10_O_BPTR	       	(OTG_DMA_BASE+0x2D0)     //  32bit dma EP10 o/p buf tx pointer
#define OTG_DMA_EP10_I_BPTR	       	(OTG_DMA_BASE+0x2D4)     //  32bit dma EP10 i/p buf tx pointer
#define OTG_DMA_EP11_O_BPTR	       	(OTG_DMA_BASE+0x2D8)     //  32bit dma EP11 o/p buf tx pointer
#define OTG_DMA_EP11_I_BPTR	       	(OTG_DMA_BASE+0x2DC)     //  32bit dma EP11 i/p buf tx pointer
#define OTG_DMA_EP12_O_BPTR	       	(OTG_DMA_BASE+0x2E0)     //  32bit dma EP12 o/p buf tx pointer
#define OTG_DMA_EP12_I_BPTR	       	(OTG_DMA_BASE+0x2E4)     //  32bit dma EP12 i/p buf tx pointer
#define OTG_DMA_EP13_O_BPTR	       	(OTG_DMA_BASE+0x2E8)     //  32bit dma EP13 o/p buf tx pointer
#define OTG_DMA_EP13_I_BPTR	       	(OTG_DMA_BASE+0x2EC)     //  32bit dma EP13 i/p buf tx pointer
#define OTG_DMA_EP14_O_BPTR	       	(OTG_DMA_BASE+0x2F0)     //  32bit dma EP14 o/p buf tx pointer
#define OTG_DMA_EP14_I_BPTR	       	(OTG_DMA_BASE+0x2F4)     //  32bit dma EP14 i/p buf tx pointer
#define OTG_DMA_EP15_O_BPTR	       	(OTG_DMA_BASE+0x2F8)     //  32bit dma EP15 o/p buf tx pointer
#define OTG_DMA_EP15_I_BPTR	       	(OTG_DMA_BASE+0x2FC)     //  32bit dma EP15 i/p buf tx pointer

#define VENDOR_ID_REG0_ADD      	OTG_I2C_BASE+0x00
#define VENDOR_ID_REG1_ADD      	OTG_I2C_BASE+0x01
#define PRODUCT_ID_REG0_ADD     	OTG_I2C_BASE+0x02
#define PRODUCT_ID_REG1_ADD     	OTG_I2C_BASE+0x03
#define MODE_REG1_SET_ADD       	OTG_I2C_BASE+0x04
#define MODE_REG1_CLR_ADD       	OTG_I2C_BASE+0x05
#define OTG_CTRL_REG1_SET_ADD   	OTG_I2C_BASE+0x06
#define OTG_CTRL_REG1_CLR_ADD  		OTG_I2C_BASE+0x07
#define INT_SRC_REG_ADD        	 	OTG_I2C_BASE+0x08
#define INT_LAT_REG_SET_ADD     	OTG_I2C_BASE+0x0a
#define INT_LAT_REG_CLR_ADD     	OTG_I2C_BASE+0x0b
#define INT_FALSE_REG_SET_ADD   	OTG_I2C_BASE+0x0c
#define INT_FALSE_REG_CLR_ADD    	OTG_I2C_BASE+0x0d