uart.c

mx21的NAND Flash Bootloader源代码

///@ingroup    NAND_BOOTLOADER
///@file uart.c
///@brief Uart operator function
///
///@author 
///@version $Version$

#ifndef _STANDALONE_
#define _STANDALONE_
#endif 

#define IO_ADDRESS 
#include "mx2.h"

#define TXFE_MASK   0x4000  // Tx buffer empty
#define RDR_MASK    0x0001  // receive data ready
//#define BIR_115200	1151
#define BIR_115200	837


typedef unsigned short u16;
/* put wemi init code here */

///Config Mx21 Uart1 Clock
void MX21_UartSetting(void)
{

 	int temp;
 	
	//only config MPCTL0 and poll the MPLLRESTART when FMCR [31:30] (CLKMODE[1:0]) = b11/b01/b10
	// PLL non bypass mode
	if (_reg_SYS_FMCR & 0xC0000000)
	{
		// 266MHz/ (1 [PRESC = b00, /1] * 3 [BCLKDIV=b0010, /3] * 2 [IPDIV=b1, /2]) 
 		// HCLK = 88MHz FLCK = 266MHz 
		
// { changed for TO2
 		temp = _reg_CRM_CSCR;
 		temp |= 0x60000000;
		_reg_CRM_CSCR = temp; //set PRESC = b11 (i.e. /4) will change to /2 later
//  changed for TO2 }
 			    	    	    
		temp = _reg_CRM_CSCR;
		temp |= 0x00000200;
		_reg_CRM_CSCR = temp;	//set IPDIV = 1, HCLK divided by 2

		temp = _reg_CRM_CSCR;
		temp &= ~0x00003C00;
		temp |= 0x00000400;	// set BCLKDIV = 1 (i.e. /2)
		//temp |= 0x00000800; 	// set BCLKDIV = 2 (i.e. /3)
		_reg_CRM_CSCR = temp;

		//PLL input 32.768kHz
		//PD = 0, MFD = 312, MFI = 7, MFN=197, PLL Output Frequency =255.9999476MHz
		//_reg_CRM_MPCTL0 = 0x01381CC5;	// 256M
		_reg_CRM_MPCTL0 = 0x007b1C73;	// 266M
		_reg_CRM_CSCR |=0x00200000;

		//wait for the MPLLRESTART bit self clear
		while (_reg_CRM_CSCR & 0x00200000);
		//_reg_CRM_CSCR &= ~0x00008000;	//set back PRESC = b01 (i.e./2)
// { changed for TO2
#if 0
		_reg_CRM_CSCR &= ~0x0000c000;	//set back PRESC = b00 (i.e./1)
#else
		_reg_CRM_CSCR &= ~0xe0000000; //set back PRESC = b000 (i.e./1)		
#endif
// changed for TO2 }
//end
	}
	else
	{
		//PLL bypass mode (MPLL = 128MHz)
		// 128MHz/ (1 [PRESC = b00, /1] * 2 [BCLKDIV=b0001, /2] * 2 [IPDIV=b1, /2]) 
		// = ipg_clk = ipg_per_clk (32MHz)
		// HCLK = 64MHz 
		// FLCK = 128MHz 
		
		temp = _reg_CRM_CSCR;
// { Changed for TO2
#if 0
		temp |= 0x0000C000;
#else
		temp &= ~0xe0000000;
		temp |= 0x60000000;
#endif
// Changed for TO2 }
		_reg_CRM_CSCR = temp;        //set PRESC = b11 (i.e. /4) will change to /1 later

		temp = _reg_CRM_CSCR;
		temp |= 0x00000200;
		_reg_CRM_CSCR = temp;     	//set IPDIV = 1

		temp = _reg_CRM_CSCR;
		temp &= ~0x00003C00;
		temp |= 0x00000400;
		_reg_CRM_CSCR = temp;        // set BCLKDIV = 1 (i.e. /2)
	 
#if 0
		_reg_CRM_CSCR &= ~0x0000C000; //set back PRESC = b00 (i.e./1)
#else
		_reg_CRM_CSCR &= ~0xe0000000; //set back PRESC = b000 (i.e./1)
#endif
	}

	// No Meaning as ipg_clk = ipg_per_clk
	// Set up PLL and Clock controller module
	// 127.9999738MHz / 4 = 31.99999346MHz
    	// set PERDIV1 to b0011 i.e. /4 
	// (***no meaning for TO1 as ipg_clk = ipg_per_clk, for TO2 only)	   
// { Changed for To2
#if 0
	_reg_CRM_PCDR |= 0x300;    
	_reg_CRM_PCDR &= ~0xC00;              
#else
        _reg_CRM_PCDR1 |= 0x5;
	_reg_CRM_PCDR1 &= 0xFFFFFFC5;
#endif	
// changed for TO2 }
	
    	//enable clock for HCLK BROM and UART_1
    	_reg_CRM_PCCR0 |= 0x10000001;

	// software reset
	_reg_UART_UCR2(UART_1) = 0x0;
	
	//write 1 to RXDMUXSEL = 1
	_reg_UART_UCR3(UART_1) |= 0x4;

	_reg_UART_UCR2(UART_2) = 0x0;
	_reg_UART_UCR3(UART_2) |= 0x4;

	//=================================================================
	// Set up GPIO/IOMUX for UART_1  
	_reg_GPIO_GIUS(GPIOE) &= 0xFFFF0FFF;	// clear bit 12-bit 15 of GIUS_E
	_reg_GPIO_GPR(GPIOE) &= 0xFFFF0FFF;	// clear bit 12-bit 15 of GPR_E

	//=================================================================

        _reg_GPIO_GIUS(GPIOE) &= ~0x00000d8;      //port E pin 3,4,6,7 for uart2
        _reg_GPIO_GPR(GPIOE) &= ~0x00000d8;       //port E pin 3,4,6,7 for primary function

	// Configure SPLL to 288MHz and usbdiv=5(/6)
	if (_reg_SYS_FMCR & 0xC0000000)  
	{
		//configure the Clock - usbdiv=5 (/6), clkdiv=0
	    	temp = _reg_CRM_CSCR;
		temp &= ~0x1C000000;
		temp |= 0x14000000;
		_reg_CRM_CSCR = temp;

		//PLL input freq = 32.768kHz
		//PLL output frequency =288 MHz USBDIV='b101, USBCLK =48M
		_reg_CRM_SPCTL0 = 0x272216d;//288Mhz
		//*(VP_U32)CRM_SPCTL0 = 0x03811C89; //240Mhz

		//set the SPLL_RESTART bit in CSCR
		_reg_CRM_CSCR |= 0x00400000;

		//wait for the SPLLRESTART bit self clear
		while (_reg_CRM_CSCR & 0x00400000);

		//wait for the SPLL Lock Flag to clear
		while (_reg_CRM_SPCTL1 & 0x00008000);

		//wait for the SPLL Lock Flag to set
		while (!(_reg_CRM_SPCTL1 & 0x00008000));

		// new PLL setting will take place
		// connect CLKO to CLK48M
		temp = _reg_CRM_CSCR;
		temp &= ~0xe0000000;
		//fma temp |= 0x40000000;
		_reg_CRM_CSCR = temp;  //gary add it according to Frank Ma's advice
                
		//gary add: change for NFC clock(/12) NAND flash programming
		temp = _reg_CRM_PCDR0;
		temp &= ~0xF000;
		temp |= 0xB000;

		_reg_CRM_PCDR0 = temp;
		
	}
	else
	{
		//PLL bypass mode (SPLL = 48MHz)
		//configure the Clock - usbdiv=0 (/1), clkdiv=0
		temp = _reg_CRM_CSCR;
		temp &= ~0x1C000000;
		_reg_CRM_CSCR = temp;   //gary add it according to Frank Ma's advice
	}
	//_reg_CRM_CSCR = temp;
	
}

///Config MX21 Uart1 As 115200-B-N-1
void MX21_InitInternalUART(void)
{
	//software reset
	_reg_UART_UCR2(UART_1) = 0x61E6;
	_reg_UART_UCR1 (UART_1)= 0x0;
	_reg_UART_UCR3(UART_1) = 0x4;
	_reg_UART_UCR4 (UART_1)= 0x8000;

	// configure appropriate pins for UART_1_RX, UART_1_TX, UART2_RX and UART2_TX		
	
	_reg_UART_UCR1 (UART_1)= 0x0005; 		// UARTEN = 1,enable the clock
	//UUCR2 = CTSC,TXEN,RXEN=1,reset, ignore IRTS bit, WS = 1 , 
	//8 bit tx and rx,1 stop bit, disable parity
	_reg_UART_UCR2(UART_1) = 0x6026;		
	_reg_UART_UCR3(UART_1) = 0x0004;		
	_reg_UART_UCR4(UART_1) = 0x8000;		

	//=================================================================
	// Set up reference freq divide for UART module 
	// MX2 only support 16MHz output
	// PerCLK1(31.99998691MHz)/UFCR[RFDIV] (2)= 15.99999673MHz
	_reg_UART_UFCR(UART_1) = 0x0A01; 	// CKIH = PerCLK1 set to div by 1 (UART 1)

	//=================================================================

	//clear loopback bit
	_reg_UART_UTS(UART_1) = 0x0000;

	//reference frequency is 16MHz
	
	//BIR_115200 = 1151
	//NUM  = 1151+1		DENOM = 9999+1
	//thus NUM/DENOM = 0.1152 --> gives baud rate: 115200		
// { Changed for TO2
#if 0
	_reg_UART_UBIR(UART_1) = BIR_115200;			// configure UBIR
#else
	 _reg_UART_UBIR(UART_1) = 837;
#endif	
// Changed for TO2
	_reg_UART_UBMR(UART_1) = 9999;				// configure UBMR
		
}

///Check if rx FIFO Ready
///@return	@li 0:		not ready
///		@li not 0:	Ready 
char EUARTdataReady()
{
    return _reg_UART_USR2(UART_1) & RDR_MASK;    // check RDR bit
}

///Send Data 
///@param data data will be sent
void EUARTputData(char data)
{
    while (!(_reg_UART_USR2(UART_1) & TXFE_MASK));    // wait until TXFE bit set
    _reg_UART_UTXD(UART_1) = (u16)data;
	 if (data == '\n')	// carriage return ? append line-feed
	 {
	    while (!(_reg_UART_USR2(UART_1) & TXFE_MASK));    // wait until TXFE bit set
   	 _reg_UART_UTXD(UART_1) = '\r';
	 }
}

///Get Data
///@return data recieved by UART
char EUARTgetData()
{
    while (!EUARTdataReady());   // wait until RDR bit set
    return (char)_reg_UART_URXD(UART_1);
}

///Put data as Hex format
///@param 	data 	data will be sent 
void EUARTputHex(unsigned char data)
{
    unsigned char  d;

    // print first digit
    d = data >> 4;
    if (d > 9)
        d += 55;
    else
        d += '0';
    EUARTputData(d);

    // print second digit
    d = data & 0xF;
    if (d > 9)
        d += 55;
    else
        d += '0';
    EUARTputData(d);
}

///put string to uart
///@param 	line		string will be sent by Uart
void EUARTputString(char *line)
{
    while (*line)
    {
        EUARTputData(*(line++));
    }
}