boot.s

mx21的NAND Flash Bootloader源代码

// size is stored in location 0x0C0000FC
	.equ SOURCE, 0xDF003200
	.equ TARGET, 0xC0003200
 	
	.global	_start
_start:

	.word   0xE59FF000
	.word   0
	.word	( _start2 - 4 )
	.word	0
	.word	( _start2 - 4 )
_loop1:	b	_loop1
	nop
	nop
	nop
	nop
	nop
	nop
	nop

_start2:
         ldr r1,=0x10000000
         ldr r3,=0x00040304
         str r3,[r1]
         
         ldr r1,=0x10020000
         ldr r3,=0x00000000
         str r3,[r1]

         ldr r1,=0x10000004
         ldr r3,=0xFFFBFCFB
         str r3,[r1]

         ldr r1,=0x10020004
         ldr r3,=0xFFFFFFFF
         str r3,[r1]        

//# Explicitly set MPLL 266MHz
//comment setmem 0x10027004 0x007b1C73 32   

         ldr r1,=0x10027004
         ldr r3,=0x007b1C73
         str r3,[r1]         

//comment comment # PLL 66MHz
//comment setmem 0x10027000 0x1700C207 32   

         ldr r1,=0x10027000
         ldr r3,=0x77000207
         str r3,[r1]      

//comment comment # PLL 88.67MHz
//setmem 0x10027000 0x17000a07 32

         ldr r1,=0x10027000
//modified for NANDFlash to use 88.67MHz
//         ldr r3,=0x17000a07
         ldr r3,=0x17000a07
         str r3,[r1]     

//comment # PLL 133MHz
//comment setmem 0x10027000 0x17000607 32

#         ldr r1,=0x10027000
#         ldr r3,=0x17000607
#         str r3,[r1]    

//comment # CS0 Initialization (Async Mode)     
//comment # 32-bit, ?? wait states              
//setmem 0xDF001000 0x00003E00 32
//setmem 0xDF001004 0x00000E01 32
        ldr r1,=0xDF001000
        ldr r3,=0x00003E00
        str r3,[r1]

       ldr r1,=0xDF001004
       ldr r3,=0x00000E01
         str r3,[r1]
//comment # Setting for Memory Map IO Port
//comment # CS1 Initialization (Async Mode)
//comment # 16-bit, D0..15, ?? wait states
//setmem 0xDF001008 0x00002000 32
//setmem 0xDF00100C 0x11118501 32
#       ldr r1,=0xDF001008
#       ldr r3,=0x00002000
#       str r3,[r1]

#       ldr r1,=0xDF00100c
#       ldr r3,=0x11118501
#       str r3,[r1]
//comment # CS3 Initialization (Async Mode)
//comment # 32-bit, ?? wait states
//setmem 0xDF001018 0x00003E00 32
//setmem 0xDF00101C 0x11110601 32
       ldr r1,=0xDF001018
       ldr r3,=0x00003E00
       str r3,[r1]
       
       ldr r1,=0xDF00101c
       ldr r3,=0x11110601
       str r3,[r1]
        
//comment # FMCR Register
//comment # Select CS3 and CSD0
//setmem 0x10027814 0xFFFFFFC9 32
  
         ldr r1,=0x10027814
         ldr r3,=0xFFFFFFC9
         str r3,[r1]          

//comment Set Precharge Command
//setmem 0xDF000000 0x92120300 32

         ldr r1,=0xDF000000
         ldr r3,=0x92120300
         str r3,[r1]    
         
//comment Issue Precharge all Command
//memory 0xC0200000 +1 32      
 
        LDR  r3, =0xC0200000 
        LDR  r2, [r3] 

//comment Set AutoRefresh Command
//setmem 0xDF000000 0xA2120300 32

        LDR  r3, =0xA2120300 
        STR  r3, [r1] 

       //  Issue AutoRefresh Command 
        LDR  r3, =0xC0000000 
        LDR  r2, [r3] 
        LDR  r2, [r3] 
        LDR  r2, [r3] 
        LDR  r2, [r3] 
        LDR  r2, [r3] 
        LDR  r2, [r3] 
        LDR  r2, [r3] 
        LDR  r2, [r3] 

//comment Set Mode Register
//setmem 0xDF000000 0xB2120300 32

        LDR  r3, =0xB2120300 
        STR  r3, [r1] 
 
//comment Issue Mode Register Command
//comment Burst Length = 8
//memory 0xC0119800 +1 32    

        LDR  r3, =0xC0119800 //; Mode Register Value 
        LDR  r2, [r3] 

//comment Set to Normal Mode
//comment # From the spec of the SDRAM K4S56163LC-RG75000, 
//comment # 1. tRCD = 19ns minimum  -> RCD = 3 clk (SDCLK=133MHz) -> SRCD = 11b 
//comment # 2. tRP  = 19ns minimum  -> RP  = 3 clk (SDCLK=133MHz) -> SRP  = 0b 
//comment # 3. tRC  = 65ns minimum  -> RC  = 9 clk (SDCLK=133MHz) -> SRC  = 1001b 
//comment # 4. refresh rate = 8192rows/64ms -> SREFR = 11b
//setmem 0xDF000000 0x8212F339 32 

        LDR  r3, =0x8212F339 
        STR  r3, [r1] 

//comment increase the driving strength for i.MX21 after 0440
		ldr	r3,=0x10027824
		ldr r0,=0x12491249
		ldr r2,=0x9

_DrivingLoop:
		str	r0,[r3]
		add	r3,r3,#4
		sub	r2,r2,#1
		teq	r2,#0
		beq	_EndDriving
		b	_DrivingLoop
		
_EndDriving:				
 
//;*************************************** 
//;*  End of SDRAM and SyncFlash Init    * 
//;*************************************** 

// copy code from FLASH to SRAM
copyCodes:
        ldr     r0,=SOURCE
        ldr     r1,=TARGET
        sub     r3,r0,#4
        ldr     r2,[r3]

_CopyLoop:
        ldr     r3,[r0]
        str     r3,[r1]
        add     r0,r0,#4
        add     r1,r1,#4
        sub     r2,r2,#4
        teq     r2,#0
        beq     _EndCopy
        b       _CopyLoop

_EndCopy:
        ldr     r0,=TARGET
        mov     pc,r0