main.c

AMIC wireless RF transceiver A7121 firmware source code.

        _nop_();
        address = address << 1;
        SpiClk = 0;
    }

    _nop_();

    //send data code
    for(i = 0; i < 16; i++)
    {
        SpiClk = 1;

        if(dataWord & 0x8000)
            SpiRxd = 1;
        else
            SpiRxd = 0;

        dataWord = dataWord<< 1;
        _nop_();
        SpiClk = 0;
    }

    _nop_();
    SpiCs = 1; //Disable A7121 SPI
    _nop_();
    SpiRxd = 1;
}

/*********************************************************************
** SpiRead
*********************************************************************/
Uint16 SpiRead(Uint8 address)
{
    Uint8 i;
    Uint16 spiData;

    spiData=0;
    SpiClk=0;
    SpiTxd = 1;

    SpiCs  = 0; //Enable A7121 SPI
    _nop_();

    //send address code
    address=(address<<2) | 0x00;//fill read bit
    for(i = 0; i < 8; i++)
    {
        SpiClk = 1;

        if(address & 0x80)
            SpiRxd = 1;
        else
            SpiRxd = 0;

        _nop_();
        address = address << 1;
        SpiClk = 0;
    }

    _nop_();

    //read data code
    for(i = 0; i < 16; i++)
    {
        SpiClk = 1;
        _nop_();

        if(SpiTxd)
            spiData = (spiData << 1) | 0x01;  // SpiRxd: read "1"
        else
            spiData = spiData << 1;           // SpiRxd: read "0"

        SpiClk = 0;
    }

    _nop_();
    SpiCs = 1;
    SpiRxd = 1;

    return spiData;
}

/*********************************************************************
*FIFOWrite
*********************************************************************/
void FIFOWrite(Uint8 source)
{
    Uint8 i;

    for(i = 0; i < 8; i++)
    {
        FIFOClk = 1;

        if(source & 0x80)
            FIFOData = 1;
        else
            FIFOData = 0;

        _nop_();
        source = source << 1;
        FIFOClk = 0;
    }

    _nop_();
    FIFOData=1;
}

/*********************************************************************
*FIFORead
*********************************************************************/
Uint8 FIFORead(void)
{
    Uint8 i;
    Uint8 tmp=0;

    for(i = 0; i < 8; i++)
    {
        FIFOClk = 1;
        _nop_();
        if(FIFOData)
            tmp = (tmp << 1) | 0x01;
        else
            tmp  = tmp << 1;

        FIFOClk = 0;
     }

     return tmp;
}

/*********************************************************************
**  SYNth_En
*********************************************************************/
void SYNth_En(void)
{
    ModeCtlReg |= 0x0004; //enable synth bit
    SpiWrite(ModeCtlReg, MODE_CONTROL_REG);
    Delay10us(15); //delay 150us for pll settling time
}

/*********************************************************************
**  SYNth_Di
*********************************************************************/
void SYNth_Di(void)
{
    ModeCtlReg &= (~0x0004); //disable synth bit
    SpiWrite(ModeCtlReg, MODE_CONTROL_REG);
}

/*********************************************************************
** ResetRF
*********************************************************************/
void ResetRF(void)
{
	//hardware reset
    ResetPin = 0;
    _nop_();
    ResetPin = 1;

    // or register reset
    //SpiWrite(0x0002,MODE_CONTROL_REG);//reset enable
	//delay();
	//SpiWrite(0x0003,MODE_CONTROL_REG);//reset disable
}

/*********************************************************************
**  FIFOWr_En
*********************************************************************/
void FIFOWr_En(void)
{
    FifoCtlReg |= 0x0004;
    SpiWrite(FifoCtlReg, FIFO_CONTROL_REG);
}

/*********************************************************************
**  FIFOWr_Di
*********************************************************************/
void FIFOWr_Di(void)
{
    FifoCtlReg &= ~0x0004;
    SpiWrite(FifoCtlReg, FIFO_CONTROL_REG);
}

/*********************************************************************
**  FIFORd_En
*********************************************************************/
void FIFORd_En(void)
{
    FifoCtlReg |= 0x0010;
    SpiWrite(FifoCtlReg, FIFO_CONTROL_REG);
}

/*********************************************************************
**  FIFORd_Di
*********************************************************************/
void FIFORd_Di(void)
{
    FifoCtlReg &= ~0x0010;
    SpiWrite(FifoCtlReg, FIFO_CONTROL_REG);
}

/*********************************************************************
** setFreq
*********************************************************************/
void SetFreq(Uint8 ch)
{
    Uint16 tmp;

    tmp = Freq_Base + ch;		//freq 2400MHz + offset ch
    tmp |= FreqBank[ch]<<13;	//find BNK[2:0] value
    SpiWrite(tmp, SYNTH1_REG);
}

/*********************************************************************
** SetTRC
*********************************************************************/
void SetTRC(Uint8 trc)
{
	if (trc)
	{
    	ModeCtlReg |= 0x0008;
    	SpiWrite(ModeCtlReg, MODE_CONTROL_REG);//set TRC=1
    }
    else
	{
	    ModeCtlReg &= (~0x0008);
	    SpiWrite(ModeCtlReg, MODE_CONTROL_REG);//set TRC=0
	}
}

/*********************************************************************
** TxPacket
*********************************************************************/
void TxPacket(void)
{
    Uint8 i;

    //write data to fifo
	FIFOWr_En();
    for (i=0; i<64; i++)
        FIFOWrite(PN9_Tab[i]);
    FIFOWr_Di();

    SetFreq(52);						//freq 2452MHz
    SetTRC(1);							//set bit TRC=1
    Ms1Pin = 1; 						//enter Tx mode
    Delay10us(6); 						//delay 60us for tx settling time

    CdTxenPin = 1; 						//start modulation
   	while(!FpRdy);						//wait until FP_RDY=1
    delay();							//delay>4us
	CdTxenPin = 0;
    Ms1Pin = 0; 						//quit Tx mode, enter synthesizer mode
}

/*********************************************************************
** RxPacket
*********************************************************************/
void RxPacket(void)
{
    Uint8 i;
    Uint8 RecvData;
    Uint8 tmp;

    Err_BitCnt=0; //clear Err_BitCnt
	FIFORd_En(); //rx fifo enable
    for (i=0; i<64; i++)
    {
        RecvData = FIFORead();

        if((RecvData ^ PN9_Tab[i])!=0)
        {
            tmp = RecvData ^ PN9_Tab[i];
            Err_BitCnt += (BitCount_Tab[tmp>>4] + BitCount_Tab[tmp & 0x0F]);
        }
    }
	FIFORd_Di(); //rx fifo disable
}

/*********************************************************************
** WaitRx
*********************************************************************/
void WaitRx(void)
{
	SetFreq(50);						//freq 2450MHz
	SetTRC(0);							//set bit TRC=0
	Ms1Pin = 1; 						//enter Rx mdoe
	while(FpRdy==0);					//wait FP_RDY=1
	Ms1Pin = 0;							//exit Rxmode, enter synthesizer mode
}

/*********************************************************************
** WaitAck
*********************************************************************/
Uint8 WaitAck(void)
{
	SetFreq(50);						//freq 2450MHz
	SetTRC(0);							//set bit TRC=0
	Ms1Pin = 1; 						//enter Rx mdoe

	Rst_Timer0();						//reload timer0
	TR0=1;								//start timer0
	while(TimeoutFlag==0 && FpRdy==0);	//wait timerout or data ready
	if (TimeoutFlag==1)
	{
		Ms1Pin=0;						//exit rx mode
		return 0;						//return 0
	}

    TR0=0;								//stop timer0
    Ms1Pin = 0;							//exit rx mode
    return 1;							//return 1
}

/*********************************************************************
** MeasureRSSI
*********************************************************************/
void MeasureRSSI(void)
{
	Uint16 tmp;
	Uint8 rssiValue;

	Ms1Pin = 1;	//enter rx mode
	Delay10us(6); //delay 60us for pll settling time

	SpiWrite(0x0005, CALIBRATION_CONTROL2_REG);	//ERSS=1
	do
	{
		tmp = SpiRead(CALIBRATION_CONTROL2_REG);
		tmp &= 0x0004;
	}
	while (tmp!=0); //check bit ERSS ok?
	Ms1Pin = 0;	//exit rx mode
	rssiValue = (SpiRead(RSSI_REG) & 0xFF00)>>8;
	_nop_();
}