📄 itcn.h

📁 MC56F802BLDC 可以使用的算法就是电机启动有点慢
💻 H
📖 第 1 页 / 共 2 页
字号:
上一页 12
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_23) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_24) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_25) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_26) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_27) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_28) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_29) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_30) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_31) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_32) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_33) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_34) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_35) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_36) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_37) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_38) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_39) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_40) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_41) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_42) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_43) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_44) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_45) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_46) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_47) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_48) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_49) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_50) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_51) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_52) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_53) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_54) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_55) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_56) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_57) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_58) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_59) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_60) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_61) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_62) | \
					 PLR_TO_IPR_MASK(ITCN_INT_PRIORITY_63) | \
					 (IRQB_TRIGGER<<3) | 0x0010*IRQB_ENABLED | \
					 IRQA_TRIGGER | 0x0002*IRQA_ENABLED \
					)
/* End of IPR mask definition */


#if (ITCN_INT_PRIORITY_10!=0)||(ITCN_INT_PRIORITY_11!=0)
	#define GPR10_TO_11 periphMemWrite(PLR_TO_GPR(0,0,ITCN_INT_PRIORITY_10,ITCN_INT_PRIORITY_11), &ArchIO.IntController.GroupPriorityReg[2])
#else
	#define GPR10_TO_11
#endif
#if (ITCN_INT_PRIORITY_12!=0)||(ITCN_INT_PRIORITY_13!=0)||(ITCN_INT_PRIORITY_14!=0)||(ITCN_INT_PRIORITY_15!=0)
	#define GPR12_TO_15 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_12,ITCN_INT_PRIORITY_13,ITCN_INT_PRIORITY_14,ITCN_INT_PRIORITY_15), &ArchIO.IntController.GroupPriorityReg[3])
#else
	#define GPR12_TO_15
#endif
#if (ITCN_INT_PRIORITY_16!=0)||(ITCN_INT_PRIORITY_17!=0)||(ITCN_INT_PRIORITY_18!=0)||(ITCN_INT_PRIORITY_19!=0)
	#define GPR16_TO_19 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_16,ITCN_INT_PRIORITY_17,ITCN_INT_PRIORITY_18,ITCN_INT_PRIORITY_19), &ArchIO.IntController.GroupPriorityReg[4])
#else
	#define GPR16_TO_19
#endif
#if (ITCN_INT_PRIORITY_20!=0)||(ITCN_INT_PRIORITY_21!=0)||(ITCN_INT_PRIORITY_22!=0)||(ITCN_INT_PRIORITY_23!=0)
	#define GPR20_TO_23 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_20,ITCN_INT_PRIORITY_21,ITCN_INT_PRIORITY_22,ITCN_INT_PRIORITY_23), &ArchIO.IntController.GroupPriorityReg[5])
#else
	#define GPR20_TO_23
#endif
#if (ITCN_INT_PRIORITY_24!=0)||(ITCN_INT_PRIORITY_25!=0)||(ITCN_INT_PRIORITY_26!=0)||(ITCN_INT_PRIORITY_27!=0)
	#define GPR24_TO_27 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_24,ITCN_INT_PRIORITY_25,ITCN_INT_PRIORITY_26,ITCN_INT_PRIORITY_27), &ArchIO.IntController.GroupPriorityReg[6])
#else
	#define GPR24_TO_27
#endif
#if (ITCN_INT_PRIORITY_28!=0)||(ITCN_INT_PRIORITY_29!=0)||(ITCN_INT_PRIORITY_30!=0)||(ITCN_INT_PRIORITY_31!=0)
	#define GPR28_TO_31 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_28,ITCN_INT_PRIORITY_29,ITCN_INT_PRIORITY_30,ITCN_INT_PRIORITY_31), &ArchIO.IntController.GroupPriorityReg[7])
#else
	#define GPR28_TO_31
#endif
#if (ITCN_INT_PRIORITY_32!=0)||(ITCN_INT_PRIORITY_33!=0)||(ITCN_INT_PRIORITY_34!=0)||(ITCN_INT_PRIORITY_35!=0)
	#define GPR32_TO_35 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_32,ITCN_INT_PRIORITY_33,ITCN_INT_PRIORITY_34,ITCN_INT_PRIORITY_35), &ArchIO.IntController.GroupPriorityReg[8])
#else
	#define GPR32_TO_35
#endif
#if (ITCN_INT_PRIORITY_36!=0)||(ITCN_INT_PRIORITY_37!=0)||(ITCN_INT_PRIORITY_38!=0)||(ITCN_INT_PRIORITY_39!=0)
	#define GPR36_TO_39 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_36,ITCN_INT_PRIORITY_37,ITCN_INT_PRIORITY_38,ITCN_INT_PRIORITY_39), &ArchIO.IntController.GroupPriorityReg[9])
#else
	#define GPR36_TO_39
#endif
#if (ITCN_INT_PRIORITY_40!=0)||(ITCN_INT_PRIORITY_41!=0)||(ITCN_INT_PRIORITY_42!=0)||(ITCN_INT_PRIORITY_43!=0)
	#define GPR40_TO_43 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_40,ITCN_INT_PRIORITY_41,ITCN_INT_PRIORITY_42,ITCN_INT_PRIORITY_43), &ArchIO.IntController.GroupPriorityReg[10])
#else
	#define GPR40_TO_43
#endif
#if (ITCN_INT_PRIORITY_44!=0)||(ITCN_INT_PRIORITY_45!=0)||(ITCN_INT_PRIORITY_46!=0)||(ITCN_INT_PRIORITY_47!=0)
	#define GPR44_TO_47 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_44,ITCN_INT_PRIORITY_45,ITCN_INT_PRIORITY_46,ITCN_INT_PRIORITY_47), &ArchIO.IntController.GroupPriorityReg[11])
#else
	#define GPR44_TO_47
#endif
#if (ITCN_INT_PRIORITY_48!=0)||(ITCN_INT_PRIORITY_49!=0)||(ITCN_INT_PRIORITY_50!=0)||(ITCN_INT_PRIORITY_51!=0)
	#define GPR48_TO_51 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_48,ITCN_INT_PRIORITY_49,ITCN_INT_PRIORITY_50,ITCN_INT_PRIORITY_51), &ArchIO.IntController.GroupPriorityReg[12])
#else
	#define GPR48_TO_51
#endif
#if (ITCN_INT_PRIORITY_52!=0)||(ITCN_INT_PRIORITY_53!=0)||(ITCN_INT_PRIORITY_54!=0)||(ITCN_INT_PRIORITY_55!=0)
	#define GPR52_TO_55 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_52,ITCN_INT_PRIORITY_53,ITCN_INT_PRIORITY_54,ITCN_INT_PRIORITY_55), &ArchIO.IntController.GroupPriorityReg[13])
#else
	#define GPR52_TO_55
#endif
#if (ITCN_INT_PRIORITY_56!=0)||(ITCN_INT_PRIORITY_57!=0)||(ITCN_INT_PRIORITY_58!=0)||(ITCN_INT_PRIORITY_59!=0)
	#define GPR56_TO_59 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_56,ITCN_INT_PRIORITY_57,ITCN_INT_PRIORITY_58,ITCN_INT_PRIORITY_59), &ArchIO.IntController.GroupPriorityReg[14])
#else
	#define GPR56_TO_59
#endif
#if (ITCN_INT_PRIORITY_60!=0)||(ITCN_INT_PRIORITY_61!=0)||(ITCN_INT_PRIORITY_62!=0)||(ITCN_INT_PRIORITY_63!=0)
	#define GPR60_TO_63 periphMemWrite(PLR_TO_GPR(ITCN_INT_PRIORITY_60,ITCN_INT_PRIORITY_61,ITCN_INT_PRIORITY_62,ITCN_INT_PRIORITY_63), &ArchIO.IntController.GroupPriorityReg[15])
#else
	#define GPR60_TO_63
#endif




#define ioctlITCN_INIT_GPRS(pItcnBase, param) { \
	GPR10_TO_11; \
	GPR12_TO_15; GPR16_TO_19; GPR20_TO_23; GPR24_TO_27; GPR28_TO_31; GPR32_TO_35; \
	GPR36_TO_39; GPR40_TO_43; GPR44_TO_47; GPR48_TO_51; GPR52_TO_55; GPR56_TO_59; \
	GPR60_TO_63; }

#define ioctlITCN_INIT_IPR(pItcnBase, param) \
	periphMemWrite(IPR_MASK, &ArchCore.InterruptPriorityReg)

#define ioctlITCN_WRITE_IPR(pItcnBase, param) \
	periphMemWrite(param, &ArchCore.InterruptPriorityReg)

#define ioctlITCN_READ_IPR(pItcnBase, param) \
	periphMemRead(&ArchCore.InterruptPriorityReg)



#define ioctlITCN_SET_INT_PRIORITY_10(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[2]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[2]); }

#define ioctlITCN_SET_INT_PRIORITY_11(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[2]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[2]); }

#define ioctlITCN_SET_INT_PRIORITY_12(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[3]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[3]); }

#define ioctlITCN_SET_INT_PRIORITY_13(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[3]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[3]); }

#define ioctlITCN_SET_INT_PRIORITY_14(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[3]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[3]); }

#define ioctlITCN_SET_INT_PRIORITY_15(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[3]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[3]); }

#define ioctlITCN_SET_INT_PRIORITY_16(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[4]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[4]); }

#define ioctlITCN_SET_INT_PRIORITY_17(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[4]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[4]); }

#define ioctlITCN_SET_INT_PRIORITY_18(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[4]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[4]); }

#define ioctlITCN_SET_INT_PRIORITY_19(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[4]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[4]); }

#define ioctlITCN_SET_INT_PRIORITY_20(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[5]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[5]); }

#define ioctlITCN_SET_INT_PRIORITY_21(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[5]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[5]); }

#define ioctlITCN_SET_INT_PRIORITY_22(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[5]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[5]); }

#define ioctlITCN_SET_INT_PRIORITY_23(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[5]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[5]); }

#define ioctlITCN_SET_INT_PRIORITY_24(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[6]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[6]); }

#define ioctlITCN_SET_INT_PRIORITY_25(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[6]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[6]); }

#define ioctlITCN_SET_INT_PRIORITY_26(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[6]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[6]); }

#define ioctlITCN_SET_INT_PRIORITY_27(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[6]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[6]); }

#define ioctlITCN_SET_INT_PRIORITY_28(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[7]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[7]); }

#define ioctlITCN_SET_INT_PRIORITY_29(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[7]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[7]); }

#define ioctlITCN_SET_INT_PRIORITY_30(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[7]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[7]); }

#define ioctlITCN_SET_INT_PRIORITY_31(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[7]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[7]); }

#define ioctlITCN_SET_INT_PRIORITY_32(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[8]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[8]); }

#define ioctlITCN_SET_INT_PRIORITY_33(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[8]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[8]); }

#define ioctlITCN_SET_INT_PRIORITY_34(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[8]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[8]); }

#define ioctlITCN_SET_INT_PRIORITY_35(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[8]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[8]); }

#define ioctlITCN_SET_INT_PRIORITY_36(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[9]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[9]); }

#define ioctlITCN_SET_INT_PRIORITY_37(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[9]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[9]); }

#define ioctlITCN_SET_INT_PRIORITY_38(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[9]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[9]); }

#define ioctlITCN_SET_INT_PRIORITY_39(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[9]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[9]); }

#define ioctlITCN_SET_INT_PRIORITY_40(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[10]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[10]); }

#define ioctlITCN_SET_INT_PRIORITY_41(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[10]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[10]); }

#define ioctlITCN_SET_INT_PRIORITY_42(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[10]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[10]); }

#define ioctlITCN_SET_INT_PRIORITY_43(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[10]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[10]); }

#define ioctlITCN_SET_INT_PRIORITY_44(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[11]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[11]); }

#define ioctlITCN_SET_INT_PRIORITY_45(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[11]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[11]); }

#define ioctlITCN_SET_INT_PRIORITY_46(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[11]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[11]); }

#define ioctlITCN_SET_INT_PRIORITY_47(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[11]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[11]); }

#define ioctlITCN_SET_INT_PRIORITY_48(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[12]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[12]); }

#define ioctlITCN_SET_INT_PRIORITY_49(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[12]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[12]); }

#define ioctlITCN_SET_INT_PRIORITY_50(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[12]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[12]); }

#define ioctlITCN_SET_INT_PRIORITY_51(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[12]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[12]); }

#define ioctlITCN_SET_INT_PRIORITY_52(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[13]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[13]); }

#define ioctlITCN_SET_INT_PRIORITY_53(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[13]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[13]); }

#define ioctlITCN_SET_INT_PRIORITY_54(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[13]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[13]); }

#define ioctlITCN_SET_INT_PRIORITY_55(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[13]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[13]); }

#define ioctlITCN_SET_INT_PRIORITY_56(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[14]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[14]); }

#define ioctlITCN_SET_INT_PRIORITY_57(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[14]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[14]); }

#define ioctlITCN_SET_INT_PRIORITY_58(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[14]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[14]); }

#define ioctlITCN_SET_INT_PRIORITY_59(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[14]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[14]); }

#define ioctlITCN_SET_INT_PRIORITY_60(pItcnBase, param) { \
	periphBitSet(param, &ArchIO.IntController.GroupPriorityReg[15]); \
	periphBitClear((~(param))&0x0007, &ArchIO.IntController.GroupPriorityReg[15]); }

#define ioctlITCN_SET_INT_PRIORITY_61(pItcnBase, param) { \
	periphBitSet((param)<<4, &ArchIO.IntController.GroupPriorityReg[15]); \
	periphBitClear((~((param)<<4))&0x0070, &ArchIO.IntController.GroupPriorityReg[15]); }

#define ioctlITCN_SET_INT_PRIORITY_62(pItcnBase, param) { \
	periphBitSet((param)<<8, &ArchIO.IntController.GroupPriorityReg[15]); \
	periphBitClear((~((param)<<8))&0x0700, &ArchIO.IntController.GroupPriorityReg[15]); }

#define ioctlITCN_SET_INT_PRIORITY_63(pItcnBase, param) { \
	periphBitSet((param)<<12, &ArchIO.IntController.GroupPriorityReg[15]); \
	periphBitClear((~((param)<<12))&0x7000, &ArchIO.IntController.GroupPriorityReg[15]); }



#define ioctlITCN_ENABLE_INT_CHANNEL(pItcnBase, param) \
	periphBitSet(param, &ArchCore.InterruptPriorityReg)

#define ioctlITCN_DISABLE_INT_CHANNEL(pItcnBase, param) \
	periphBitClear(param, &ArchCore.InterruptPriorityReg)

#define ioctlITCN_ENABLE_IRQ(pItcnBase, param) \
	periphBitSet((param), &ArchCore.InterruptPriorityReg)

#define ioctlITCN_DISABLE_IRQ(pItcnBase, param) \
	periphBitClear(param, &ArchCore.InterruptPriorityReg)

#define ioctlITCN_IRQA_TRIGGER_MODE(pItcnBase, param) { \
	periphBitSet((param & (ITCN_IPR_IAINV | ITCN_IPR_IAL1)), &ArchCore.InterruptPriorityReg); \
	periphBitClear(((~param) & (ITCN_IPR_IAINV | ITCN_IPR_IAL1)), &ArchCore.InterruptPriorityReg); }

#define ioctlITCN_IRQB_TRIGGER_MODE(pItcnBase, param) { \
	periphBitSet((((param)<<3) & (ITCN_IPR_IBINV | ITCN_IPR_IBL1)), &ArchCore.InterruptPriorityReg); \
	periphBitClear(((~((param)<<3)) & (ITCN_IPR_IBINV | ITCN_IPR_IBL1)), &ArchCore.InterruptPriorityReg); }

#endif
上一页 12
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -