occs.h

来自「MC56F802BLDC 可以使用的算法就是电机启动有点慢」· C头文件代码 · 共 280 行
280 行
/*******************************************************************************
*
*  Motorola Inc.
*  (c) Copyright 2000 Motorola Inc.
*  ALL RIGHTS RESERVED.
*
********************************************************************************
*
*
*  File Name:   occs.h
*
*  Description: Header file for On-chip Clock Synthesis (OCCS) driver.
*
*
*  Modules Included:
*
*  Notes: 
*
*
*******************************************************************************/
#ifndef __OCCS_H
#define __OCCS_H



/*******************************************************************************
	OCCS base address used as device handle in ioctl()
*******************************************************************************/
#define OCCS					(&ArchIO.Pll)



/*******************************************************************************
	Defines for appconfig.h
********************************************************************************
	#define EXTCLK						8000000UL		oscillator frequency

	void occsISR(void);
	#define INT_VECTOR_ADDR_62				occsISR
	#define ITCN_INT_PRIORITY_62			value 0 to 7 (0 means interrupt is disabled)

	#define OCCS_CONTROL_REG				0x0000
	#define OCCS_DIVIDE_BY_REG				0x0000
	#define OCCS_CLKO_SELECT_REG			0x0000
	#define OCCS_INTERNAL_OSC_REG			0x0000 (only for 801)
*/


/*  Equations for calculating Prescaler, Postscaler, DivBy according to
	needed Fosc and Fzclk:
	1) ZCLK - Postscaler output
		Fvco = Fosc*(DivBy+1)/Prescaler		(VCO frequency)
		Fzclk = Fvco/(2*Postscaler)			(ZCLK frequency, 
											 what is DSP core frequency)
	2) ZCLK - Prescaler output
		Fzclk = Fosc/Prescaler
	Recommended range of Fvco is 80MHz to 240MHz.
	The maximum Fzclk is 80MHz.
	IP Bus clock frequency is Fzclk divided by 2.
*/



/*******************************************************************************
	ioctl() commands
********************************************************************************
		command						parameters and commentary */
#define OCCS_INIT					/* NULL , occsInit function is called (initialization) */
#define OCCS_SET_CORE_CLOCK			/* OCCS_CLOCK_IN_DIVIDE_BY_x | OCCS_CLOCK_OUT_DIVIDE_BY_y | DivBy,
									where x and y are 1,2,4 or 8. Range of DivBy is 0 to 127
									After command is executed the VCO frequency and DSP core frequency is
									Fvco = Fosc*(DivBy+1)/Prescaler
									Fzclk = Fvco/(2*Postscaler)
									(recommended range of Fvco is 80MHz to 240MHz) */
#define OCCS_SET_POSTSCALER			/* OCCS_CLOCK_OUT_DIVIDE_BY_x, where x is 1,2,4 or 8 */
#define OCCS_SET_PRESCALER			/* OCCS_CLOCK_IN_DIVIDE_BY_x, where x is 1,2,4 or 8 
									use this command only when ZCLOCK Source is set to prescaler */
#define OCCS_SET_DIVIDE_BY			/* value  0 to 127, use this command only when ZCLOCK Source is set to prescaler */
#define OCCS_SET_LORTP				/* value  1 to 15 */
#define OCCS_ENABLE_INT				/* (OCCS_INT1_ANY_EDGE / OCCS_INT1_FALLING_EDGE / OCCS_INT1_RISING_EDGE) |
									(OCCS_INT0_ANY_EDGE / OCCS_INT0_FALLING_EDGE / OCCS_INT0_RISING_EDGE) |
									OCCS_LOSS_OF_CLOCK_INT */
#define OCCS_DISABLE_INT			/* OCCS_INT1 |	OCCS_INT0 | OCCS_LOSS_OF_CLOCK_INT */
#define OCCS_LOCK_DETECTOR			/* OCCS_ENABLE / OCCS_DISABLE */
#define OCCS_TURN_OFF_CHARGE_PUMP	/* NULL, use this command only in the event of loss of clock */
#define OCCS_SET_PRESC_CLOCK_SEL	/* OCCS_CRYSTAL_OSC / OCCS_INTERNAL_RELAX_OSC, !this command is available only on DSP56F801, if you want crystal oscillator GPIOB2 and GPIOB3 must be set as peripheral (not GPIO), what is default after reset */
#define OCCS_SET_ZCLOCK_SOURCE		/* OCCS_PRESCALER_OUTPUT / OCCS_POSTSCALER_OUTPUT */
#define OCCS_GET_ZCLOCK_SOURCE		/* NULL, returns OCCS_PRESCALER_OUTPUT or OCCS_POSTSCALER_OUTPUT or 0x0000 or 0x0011,
									value 0x0000 or 0x0011 means synchronizing is in progress */
#define OCCS_SELECT_CLKO			/* OCCS_ZCLK / OCCS_NO_CLK */
#define OCCS_READ_FLAG				/* OCCS_STATUS_LOCK_LOST_INT1 | OCCS_STATUS_LOCK_LOST_INT0 |
									OCCS_STATUS_CLOCK_LOST (| OCCS_STATUS_LOCK_1 | OCCS_STATUS_LOCK_0)
									returns 0 if flag is cleared, non-zero if flag is set */
#define OCCS_CLEAR_FLAG				/* OCCS_STATUS_LOCK_LOST_INT1 | OCCS_STATUS_LOCK_LOST_INT0 |
									OCCS_STATUS_CLOCK_LOST */
#define OCCS_RELAX_OSC				/* OCCS_ENABLE / OCCS_DISABLE, only for 801 */
#define OCCS_ADJUST_RELAX_OSC_FREQ	/* value of 0 to 255, only for 801 */
#define OCCS_GET_IPBUS_FREQ			/* oscillator frequency [Hz](UInt32), returns IPBus Clock frequency [Hz] (UInt32) */


#define OCCS_WRITE_CONTROL_REG		/* 16 bit value */
#define OCCS_WRITE_DIVIDE_BY_REG	/* 16 bit value */
#define OCCS_WRITE_STATUS_REG		/* 16 bit value */
#define OCCS_WRITE_INTERNAL_OSC_REG	/* 16 bit value */

#define OCCS_READ_CONTROL_REG		/* NULL, returns UWord16 */
#define OCCS_READ_DIVIDE_BY_REG		/* NULL, returns UWord16 */
#define OCCS_READ_STATUS_REG		/* NULL, returns UWord16 */
#define OCCS_READ_INTERNAL_OSC_REG	/* NULL, returns UWord16 */





/*******************************************************************************
	Register bits
*******************************************************************************/
/* OCCS CONTROL REGISTER FLAGS */
#define OCCS_INT1_ANY_EDGE				0xC000
#define OCCS_INT1_FALLING_EDGE			0x8000
#define OCCS_INT1_RISING_EDGE			0x4000
#define OCCS_INT0_ANY_EDGE				0x3000
#define OCCS_INT0_FALLING_EDGE			0x2000
#define OCCS_INT0_RISING_EDGE			0x1000
#define OCCS_LOSS_OF_CLOCK_INT			0x0800
#define OCCS_LOCK_DETECTOR_BIT			0x0080
#define OCCS_CHARGE_PUMP_FLAG			0x0040
#define OCCS_POWER_DOWN					0x0010	// this bit is not used in revision B chip
#define OCCS_PRESCALER_CLOCK_SELECT		0x0004	// only for DSP56F801, for 803,805 and 807 it is reserved (value 0)
#define OCCS_ZCLOCK_PRESCALER			0x0001
#define OCCS_ZCLOCK_POSTSCALER			0x0002

/* OCCS DIVIDE-BY REGISTER FLAGS */
#define OCCS_CLOCK_OUT_DIVIDE_BY_1      0x0000
#define OCCS_CLOCK_OUT_DIVIDE_BY_2      0x0400
#define OCCS_CLOCK_OUT_DIVIDE_BY_4      0x0800
#define OCCS_CLOCK_OUT_DIVIDE_BY_8      0x0C00
#define OCCS_CLOCK_IN_DIVIDE_BY_1       0x0000
#define OCCS_CLOCK_IN_DIVIDE_BY_2       0x0100
#define OCCS_CLOCK_IN_DIVIDE_BY_4       0x0200
#define OCCS_CLOCK_IN_DIVIDE_BY_8       0x0300

/* OCCS STATUS REGISTER FLAGS */
#define OCCS_STATUS_LOCK_LOST_INT1      0x8000
#define OCCS_STATUS_LOCK_LOST_INT0      0x4000
#define OCCS_STATUS_CLOCK_LOST          0x2000
#define OCCS_STATUS_LOCK_1              0x0040
#define OCCS_STATUS_LOCK_0              0x0020
#define OCCS_STATUS_POWERED_DOWN        0x0010
#define OCCS_STATUS_ZCLOCK_PRESCALER    0x0001
#define OCCS_STATUS_ZCLOCK_POSTSCALER   0x0002

/* OCCS CLKO SELECT REGISTER FLAGS */
#define OCCS_ZCLK       			    0x0000
#define OCCS_NO_CLK						0x0010

/* OCCS INTERNAL OSCILLATOR CONTROL REGISTER FLAGS (only for 801) */
#define OCCS_RELAX_OSC_POWERDOWN_FLAG	0x8000

/* */
#define OCCS_CRYSTAL_OSC				true
#define OCCS_INTERNAL_RELAX_OSC			false
#define OCCS_INT1						0xC000
#define OCCS_INT0						0x3000
#define OCCS_PRESCALER_OUTPUT			0x0001
#define OCCS_POSTSCALER_OUTPUT			0x0002

/* enable/disable */
#define OCCS_ENABLE						true
#define OCCS_DISABLE					false




/* Function prototypes */
void occsInit(void);
UInt32 occsGetIPBusFreq(UInt32 OscFreq);
/* Function parameters: OscFreq - oscillator frequency [Hz]
   Function returns IP Bus frequency [Hz]. */




/*******************************************************************************
	Implementations of OCCS ioctl() commands
*******************************************************************************/
#define ioctlOCCS_INIT(pOccsBase,param)		occsInit()

#define ioctlOCCS_SET_CORE_CLOCK(pOccsBase,param) \
	{ \
		periphMemWrite(OCCS_LOCK_DETECTOR_BIT | OCCS_ZCLOCK_PRESCALER, \
					   (UWord16 *)(&((arch_sPLL*)pOccsBase)->ControlReg)); \
		periphMemWrite(0x2000 | param, (UWord16 *)(&((arch_sPLL*)pOccsBase)->DivideReg)); \
		/* Wait until PLL is locked */ \
		while (!periphBitTest(OCCS_STATUS_LOCK_1, (UWord16 *)(&((arch_sPLL*)pOccsBase)->StatusReg))) \
			; \
		periphMemWrite(OCCS_LOCK_DETECTOR_BIT | OCCS_ZCLOCK_POSTSCALER, \
					   (UWord16 *)(&((arch_sPLL*)pOccsBase)->ControlReg)); \
	}

#define ioctlOCCS_SET_POSTSCALER(pOccsBase, param) \
	{ periphBitSet(param & 0x0C00, (UWord16 *)(&((arch_sPLL*)pOccsBase)->DivideReg)); \
	  periphBitClear((~param) & 0x0C00, (UWord16 *)(&((arch_sPLL*)pOccsBase)->DivideReg)); }

#define ioctlOCCS_SET_PRESCALER(pOccsBase, param) \
	{ periphBitSet(param & 0x0300, (UWord16 *)(&((arch_sPLL*)pOccsBase)->DivideReg)); \
	  periphBitClear((~param) & 0x0300, (UWord16 *)(&((arch_sPLL*)pOccsBase)->DivideReg)); }

#define ioctlOCCS_SET_DIVIDE_BY(pOccsBase, param) \
	{ periphBitSet(param & 0x007F, (UWord16 *)(&((arch_sPLL*)pOccsBase)->DivideReg)); \
	  periphBitClear((~param) & 0x007F, (UWord16 *)(&((arch_sPLL*)pOccsBase)->DivideReg)); }

#define ioctlOCCS_SET_LORTP(pOccsBase, param) \
	{ periphBitSet((param << 12) & 0xF000, (UWord16 *)(&((arch_sPLL*)pOccsBase)->DivideReg)); \
	  periphBitClear((~(param << 12)) & 0xF000, (UWord16 *)(&((arch_sPLL*)pOccsBase)->DivideReg)); }

#define ioctlOCCS_SELECT_CLKO(pOccsBase, param) \
	periphMemWrite(param, (UWord16 *)(&((arch_sPLL*)pOccsBase)->SelectReg))

#define ioctlOCCS_TURN_OFF_CHARGE_PUMP(pOccsBase, param) \
	periphBitSet(OCCS_CHARGE_PUMP_FLAG, (UWord16 *)(&((arch_sPLL*)pOccsBase)->ControlReg))

#define ioctlOCCS_ENABLE_INT(pOccsBase, param) \
	periphBitSet(param, (UWord16 *)(&((arch_sPLL*)pOccsBase)->ControlReg))

#define ioctlOCCS_SET_ZCLOCK_SOURCE(pOccsBase, param) \
	{ periphMemWrite( periphMemRead((UWord16 *)(&((arch_sPLL*)pOccsBase)->ControlReg)) & 0xFFFC | param, (UWord16 *)(&((arch_sPLL*)pOccsBase)->ControlReg) ); }

#define ioctlOCCS_GET_ZCLOCK_SOURCE(pOccsBase, param) \
	periphBitTest(0x0003, (UWord16 *)(&((arch_sPLL*)pOccsBase)->StatusReg))

#define ioctlOCCS_DISABLE_INT(pOccsBase, param) \
	periphBitClear(param, (UWord16 *)(&((arch_sPLL*)pOccsBase)->ControlReg))

#define ioctlOCCS_READ_FLAG(pOccsBase, param) \
	periphBitTest(param, (UWord16 *)(&((arch_sPLL*)pOccsBase)->StatusReg))

#define ioctlOCCS_CLEAR_FLAG(pOccsBase, param) \
	periphBitSet(param, (UWord16 *)(&((arch_sPLL*)pOccsBase)->StatusReg))

#define ioctlOCCS_GET_IPBUS_FREQ(pOccsBase,param)	occsGetIPBusFreq(param)

#define ioctlOCCS_LOCK_DETECTOR(pOccsBase, param) \
	if (param) {periphBitSet(OCCS_LOCK_DETECTOR_BIT, (UWord16 *)(&((arch_sPLL*)pOccsBase)->ControlReg));} \
	else		{periphBitClear(OCCS_LOCK_DETECTOR_BIT, (UWord16 *)(&((arch_sPLL*)pOccsBase)->ControlReg));}



/* Reading(writing) from(to) registers */
#define ioctlOCCS_WRITE_CONTROL_REG(pOccsBase,param) \
	periphMemWrite(param, (UWord16 *)(&((arch_sPLL*)pOccsBase)->ControlReg))

#define ioctlOCCS_WRITE_DIVIDE_BY_REG(pOccsBase,param) \
	periphMemWrite(param, (UWord16 *)(&((arch_sPLL*)pOccsBase)->DivideReg))

#define ioctlOCCS_WRITE_STATUS_REG(pOccsBase,param) \
	periphMemWrite(param, (UWord16 *)(&((arch_sPLL*)pOccsBase)->StatusReg))



#define ioctlOCCS_READ_CONTROL_REG(pOccsBase,param) \
	periphMemRead((UWord16 *)(&((arch_sPLL*)pOccsBase)->ControlReg))

#define ioctlOCCS_READ_DIVIDE_BY_REG(pOccsBase,param) \
	periphMemRead((UWord16 *)(&((arch_sPLL*)pOccsBase)->DivideReg))

#define ioctlOCCS_READ_STATUS_REG(pOccsBase,param) \
	periphMemRead((UWord16 *)(&((arch_sPLL*)pOccsBase)->StatusReg))





/**********************************************************************
* Include of device specific OCCS commands and defines
***********************************************************************/
#include "occstarget.h"  /* device specific defines */


#endif
occs.h - 源码说明

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