appconfig.h

来自「MC56F802BLDC 可以使用的算法 就是电机启动有点慢」· C头文件 代码 · 共 250 行

/*****************************************************************************
*
* Motorola Inc.
* (c) Copyright 2000 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
******************************************************************************
*
* File Name: appconfig.h
*
* Description: file for static configuration of the application
*              (initial values, interrupt vectors)
*
* Modules Included:
*
*****************************************************************************/

#ifndef __APPCONFIG_H
#define __APPCONFIG_H

/*.********************************************************************
*
*    RADEGAST configuration file generated by Hawk Configuration Tool
*
***********************************************************************.*/

#define   DSP56F802
#define   EXTCLK   8000000L


/*. 
    OCCS, COP & External interrupts  configuration
    -------------------------------------------
    Core freq.=76.000 MHz, IPBus freq.=38.000 MHz
    COP disabled, COP period =0.22 ms
    External interrupts:  IRQA, IRQB
.*/
#define OCCS_DIVIDE_BY_REG         0x0012		 //原来程序是 0x0012
extern void isrIRQA(void);
#define INT_VECTOR_ADDR_8          isrIRQA
extern void isrIRQB(void);
#define INT_VECTOR_ADDR_9          isrIRQB
#define IRQA_ENABLED               0x0001
#define IRQB_ENABLED               0x0001
#define IRQA_TRIGGER               0x0004
#define IRQB_TRIGGER               0x0004


/*. 
    Quad Timer A2 configuration
    ----------------------------
    Count mode: Count rising edges of primary source
    Primary count source: Prescaler (IP BUS clock divide by 64)
    Secondary count source: Counter #0 input pin
    Input polarity: True polarity
    Output polarity: True polarity
    Input capture mode: Load the capture register on rising edge of input
    Output capture mode: Asserted while counter is active
    Count once: Count repeatedly
    Count direction: Count up
    Coinit disabled, Master mode disabled, Output disabled
    Interrupts:  None
.*/
#define QT_C2_CONTROL_REG          0x3c00
#define QT_C2_STATUS_CONTROL_REG   0x0040
extern void isrQT_C2(void);
#define INT_VECTOR_ADDR_36         isrQT_C2
#define ITCN_INT_PRIORITY_36       0x0001


/*. 
    Quad Timer A3 configuration
    ----------------------------
    Count mode: Count rising edges of primary source
    Primary count source: Prescaler (IP BUS clock divide by 1)
    Secondary count source: Counter #0 input pin
    Input polarity: True polarity
    Output polarity: True polarity
    Input capture mode: Capture disabled, input edge flag INTdisabled
    Output capture mode: Asserted while counter is active
    Count once: Count repeatedly
    Count direction: Count up
    Coinit disabled, Master mode disabled, Output disabled
    Interrupts:  None
.*/
#define QT_C3_CONTROL_REG          0x3020
extern void isrQT_C3(void);
#define INT_VECTOR_ADDR_37         isrQT_C3
#define ITCN_INT_PRIORITY_37       0x0001


/*. 
    Quad Timer D1 configuration
    ----------------------------
    Count mode: Count rising edges of primary source
    Primary count source: Prescaler (IP BUS clock divide by 16)
    Secondary count source: Counter #0 input pin
    Input polarity: True polarity
    Output polarity: True polarity
    Input capture mode: Load the capture register on rising edge of input
    Output capture mode: Asserted while counter is active
    Count once: Count repeatedly
    Count direction: Count down
    Coinit disabled, Master mode disabled, Output disabled
    Interrupts:  Compare interrupt
.*/
#define QT_D1_CONTROL_REG          0x7CB0//原来的0x3830
#define QT_D1_STATUS_CONTROL_REG   0x0480//原来的：0x4040          /*Compare Interrupt Enable */
#define QT_D1_LOAD_REG             0xffff          /*45000D */
#define QT_D1_COUNTER_REG          0xffff          /*must be the same as load register */
extern void isrQT_D1(void);
#define INT_VECTOR_ADDR_31         isrQT_D1        /*Timer D1 Interrupt Service Routine */
#define ITCN_INT_PRIORITY_31       0x0001


/*. 
    Analog to digital converter A configuration
    --------------------------------------------
    Clock frequency = 2.375 MHz
    Trigger source: Software start
    Scan mode: Once Simultaneous
    Sample 0 mapped to AN2, zero crossing enabled for any change
    Sample 1 mapped to AN3, zero crossing enabled for any change
    Sample 2 mapped to AN4, zero crossing enabled for any change
    Sample 4 mapped to AN0, zero crossing disabled电压
    Sample 5 mapped to AN1, zero crossing disabled
    Sample 6 mapped to AN5, zero crossing disabled
    Interrupts:  End of scan, Zero crossing, Low limit, High limit
.*/
#define ADC_A_CONTROL_REG1         0x4f01
#define ADC_A_ZERO_CROSS_CONTROL_REG 0x003f//#define ADC_A_ZERO_CROSS_CONTROL_REG 0x003f 2月17我修改
#define ADC_A_CHANNEL_LIST_REG1    0x3432//#define ADC_A_CHANNEL_LIST_REG1    0x3432 2月19我修改
#define ADC_A_CHANNEL_LIST_REG2    0x7676//#define ADC_A_CHANNEL_LIST_REG2    0x7510  2月19我修改
#define ADC_A_SAMPLE_DISABLE_REG   0x0000//#define ADC_A_SAMPLE_DISABLE_REG   0x0088  2月17我修改
extern void isrADC_A_EndOfScan(void);
#define INT_VECTOR_ADDR_55         isrADC_A_EndOfScan
#define ITCN_INT_PRIORITY_55       0x0002
extern void isrADC_A_Limit(void);
#define INT_VECTOR_ADDR_57         isrADC_A_Limit
#define ITCN_INT_PRIORITY_57       0x0001


/*. 
    PWM A configuration
    --------------------
    PWM clock period = 26.316 ns, PWM period = 100000.000 ns
    PWM freq = 10.000 kHz, Dead time = 447.368 us
    Alignment: Center
    PWM reload frequency: Every opportunity, Halfcycle reload: disabled
    Correction method: Manual Correction (No correction)
    Value register load mode: Writing to value register 0 also writes to 0-5
    Ch 0-1 Polarity - Top: Positive, Bottom: Positive; Operation: Independent
    Ch 2-3 Polarity - Top: Positive, Bottom: Positive; Operation: Independent
    Ch 4-5 Polarity - Top: Positive, Bottom: Positive; Operation: Independent
    Load OK: enabled
    Interrupts:     Load OK: enabled
.*/
#define PWM_A_CONTROL_REG          0x0003
#define PWM_A_COUNTER_MODULO_REG   0x03B6
#define PWM_A_DEAD_TIME_REG        0x0011
#define PWM_A_DISABLE_MAPPING_1_REG 0x1111
#define PWM_A_DISABLE_MAPPING_2_REG 0x0011
#define PWM_A_CONFIG_REG           0x077e//#define PWM_A_CONFIG_REG           0x000e原来的程序是正逻辑，现在改成负逻辑
                                         //000e用于MOT的功率驱动板，077e用于自己的功率驱动板
#define PWM_A_CHANNEL_CONTROL_REG  0x007f
extern void isrPWM_A_Reload(void);
#define INT_VECTOR_ADDR_59         isrPWM_A_Reload
#define ITCN_INT_PRIORITY_59       0x0003
extern void isrPWM_A_Fault(void);
#define INT_VECTOR_ADDR_61         isrPWM_A_Fault
#define ITCN_INT_PRIORITY_61       0x0001


/*. 
    Serial communication interface 0 configuration
    -----------------------------------------------
    Baud rate: 9615.4 Bd
    Receiver: enabled
    Transmitter: enabled
    Data word length: 8 bits
    Parity: None
    Polarity: True polarity
    Wake-up condition: By idle
    Wait mode function: SCI disabled in Wait Mode
    Loop mode: Disabled
    Interrupts:  RX error, RX full
.*/
#define SCI_0_BAUD_RATE_REG        0x00f7
#define SCI_0_CONTROL_REG          0x003c
extern void pcmasterRxTxIsr(void);
#define INT_VECTOR_ADDR_51         pcmasterRxTxIsr /*SCI 0 Tx Empty Interrupt */
#define ITCN_INT_PRIORITY_51       0x0001
extern void pcmasterRxTxIsr(void);
#define INT_VECTOR_ADDR_53         pcmasterRxTxIsr /*SCI 0 Rx Full Interrupt */
#define ITCN_INT_PRIORITY_53       0x0001
extern void pcmasterRxErrorIsr(void);
#define INT_VECTOR_ADDR_52         pcmasterRxErrorIsr /*SCI 0 Rx Error Interrupt */
#define ITCN_INT_PRIORITY_52       0x0002


/*. 
    GPIO B configuration
    ---------------------
    Pin 0 - Direction: Output, Mode: GPIO, Pull-up: Enable
    Pin 1 - Direction: Output, Mode: GPIO, Pull-up: Enable
    Pin 2 - Direction: Output, Mode: GPIO, Pull-up: Enable
    Pin 3 - Direction: Input, Mode: Peripheral, Pull-up: Disable
    Pin 4 - Direction: Input, Mode: Peripheral, Pull-up: Disable
    Pin 5 - Direction: Input, Mode: Peripheral, Pull-up: Disable
    Pin 6 - Direction: Input, Mode: Peripheral, Pull-up: Disable
    Pin 7 - Direction: Input, Mode: Peripheral, Pull-up: Disable
    GPIO interrupt disabled
.*/
#define GPIO_B_PULLUP_ENABLE_REG   0x00f8
#define GPIO_B_DATA_DIRECTION_REG  0x0007
#define GPIO_B_PERIPHERAL_ENABLE_REG 0x00f8


/*. 
    GPIO D configuration
    ---------------------
    Pin 0 - Direction: Input, Mode: Peripheral, Pull-up: Disable
    Pin 1 - Direction: Input, Mode: Peripheral, Pull-up: Disable
    Pin 2 - Direction: Input, Mode: Peripheral, Pull-up: Disable
    Pin 3 - Direction: Input, Mode: Peripheral, Pull-up: Disable
    Pin 4 - Direction: Input, Mode: Peripheral, Pull-up: Disable
    Pin 5 - Direction: Input, Mode: GPIO, Pull-up: Enable
    Pin 6 - Direction: Input, Mode: Peripheral, Pull-up: Disable
    Pin 7 - Direction: Input, Mode: Peripheral, Pull-up: Disable
    GPIO interrupt disabled
.*/
#define GPIO_D_PULLUP_ENABLE_REG   0x00df
#define GPIO_D_PERIPHERAL_ENABLE_REG 0x00df


/*.
    User definitions
    ----------------- 
.*/
//#define   PCMASTER_INCLUDE_CMD_SCOPE               /* Read scope, Setup scope */
//#define   PCMASTER_INCLUDE_CMD_RECORDER            /* Setup recorder, */
//#define   PCMASTER_INCLUDE_CMD_APPCMD              /* Call app comd, */
//#define   PCMASTER_BUFFER_SIZE     1              /* PC Master input/output buffer size */
//#define   PCMASTER_REC_BUFF_LEN    1             /* recorder buffer length */


/*.         End of autogenerated code
*************************************************** ..*/

#endif