spi.h

来自「MC56F802BLDC 可以使用的算法就是电机启动有点慢」· C头文件代码 · 共 330 行
330 行
/*****************************************************************************
*
* Motorola Inc.
* (c) Copyright 2001 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
******************************************************************************
*
* File Name: spi.h
*
* Description: SPI driver macros and definitions
*
* Modules Included: none
*
*****************************************************************************/

#ifndef __SPI_H
#define __SPI_H

/************************************************************
* SPI module identifiers, correspond to module base address
*************************************************************/

#define SPI_0 (&ArchIO.Spi)


/***************************************************
* SPI Ioctl commands
****************************************************/
/* command                    |        Param       */

/* SPI status and control register commands */
#define SPI_INIT                /* NULL */
#define SPI_DEVICE				/* SPI interface enable(1)/disable(1) */

#define SPI_SET_MODE			/* MASTER(1) / SLAVE(0) */

/* set DSO bit - determines which bit is transmitted or received first */
#define SPI_SET_ORDER	 	    /* LSB first(1) / MSB first(0) */

/* set CPOL bit - determine which edge shifts out data */
#define SPI_SET_CLOCK_POLARITY  /* rising edge start(1) / falling edge start(0) */

/* set CPHA bit - required state of /SS pin between transmitions */
#define SPI_SET_CLOCK_PHASE	    /* first SCLK edge starts slave transmission(1) / /SS falling edge starts slave transmission(0) */

/* set MODFEN bit */
#define SPI_SET_MODE_FAULT		/* mode fault enable(1)/disable(0) */

/* interrrupts enable disable */
#define SPI_RX_FULL_INT			/* receive interrupt enable(1)/disable(0) */
#define SPI_TX_EMPTY_INT		/* transmit interrupt enable(1)/disable(0) */
#define SPI_ERROR_INT			/* error (overflow/mode fault) interrupt ON(1)/OFF(0) */

/* SPI data size register set */
#define SPI_SET_DATA_SIZE 		/* UWord16:4 - (data size - 1) */
#define SPI_SET_BAUD_DIV 		/* UWord16:2 - baud rate divisor */
                                /* - use constants SPI_DIVx or shift num <<6 */
								/* Baud rate = IPBus_clk/rate_divisor */

/* write transmit register */
#define SPI_WRITE		/* UWord16: transmit data 2-16bits */
/* read receive register */
#define SPI_READ			/* NULL */

/* test SPI status bits - can be used directly in condition */
/* if it is used in assignement then it returns bit value in original bit position */
/* all bits are read only */
/* test SPTE bit */
#define SPI_GET_TX_EMPTY		/* NULL */
/* test SPRF bit */
#define SPI_GET_RX_FULL			/* NULL */
/* test OVRF bit */
#define SPI_GET_RX_OVERFLOW		/* NULL */
/* test MODF bit */
#define SPI_GET_MODE_FAULT		/* NULL */

#define SPI_GET_ERROR	        /* NULL */

#define SPI_CLEAR_MODE_FAULT	/* NULL */
#define SPI_CLEAR_RX_OVERFLOW	/* NULL */

/* clear SPI interrupt flags - are cleared automatically by reading RX or write TX */
/* => not implemented */

/* commands for read, write functions control - it reads and writes */
/* spi0_status and associated variables used for read, write functions */
#define SPI_CLEAR_EXCEPTION		/* NULL */
#define SPI_GET_STATUS			/* NULL */
#define SPI_WRITE_CANCEL		/* NULL */
#define SPI_READ_CANCEL			/* NULL */

/****************************************************************************
* SPI constants and type declarations used in the ioctl functions
*****************************************************************************/

#define SPI_ENABLE	1
#define SPI_DISABLE	0

#define SPI_RISING_EDGE		1
#define SPI_FALLING_EDGE 	0

#define SPI_SCLK_EDGE 	1
#define SPI_SS_EDGE 	0


/* status generated by read/write functions -> check by SPI0_GET_STATUS command */
#define SPI_STATUS_WRITE_INPROGRESS		0x0001    /* write to SPI is in progress */
#define SPI_STATUS_READ_INPROGRESS		0x0002    /* read from SPI is in progress */

#define SPI_STATUS_EXCEPTION_EXIST		0x0010    /* exception exists - HW exception if only this flag is set
                                                           - SW exception if other exception flags are set */
#define SPI_EXCEPTION_BUFFER_OVERFLOW	0x0020    /* buffer overflow - some bytes were thrown away */

/* exception codes */
#define SPI_EXCEPTION_OVERRUN   		0x0040
#define SPI_EXCEPTION_MODE_FAULT   		0x0080

/* constants and bit masks */

/* SPI_SET_BAUD_DIV */
#define SPI_DIV2   0x0000
#define SPI_DIV8   0x0040
#define SPI_DIV16  0x0080
#define SPI_DIV32  0x00C0

/* SPI_MSB_LSB_ORDER */
#define SPI_MSB_FIRST   0
#define SPI_LSB_FIRST   1

/* SPI_MODE */
#define SPI_MASTER   1
#define SPI_SLAVE    0

/* bit masks for registers settings */
/* status and control register */

#define SPI_SPE		0x0002
#define SPI_SPTIE	0x0001
#define SPI_CPHA	0x0004
#define SPI_CPOL	0x0008
#define SPI_SPMSTR	0x0010
#define SPI_SPRIE	0x0020
#define SPI_MODFEN	0x0100
#define SPI_ERRIE	0x1000
#define SPI_DSO		0x4000

/* read only */
#define SPI_SPTE	0x0200
#define SPI_MODF	0x0400	/* can be writed by "1" to clear it */
#define SPI_OVRF	0x0800
#define SPI_SPRF	0x2000


/****************************************************************************
* SPI function prototypes
*****************************************************************************/

extern void spiInit(arch_sSPI *pSpiBase);

extern void Spi0TxEmptyISR(void);
extern void Spi0ReceiveISR(void);
extern void write_SPI_0_NON_BLOCKING(const void *buf, unsigned char size);
extern void read_SPI_0_NON_BLOCKING(void *buf, unsigned char size);
extern void write_SPI_0_BLOCKING(const void *buf, unsigned char size);
extern void read_SPI_0_BLOCKING(void *buf, unsigned char size);


/***********************************************************************
* status variables for read/wrire functions
***********************************************************************/

extern volatile UWord16 spi0_status;
extern volatile UWord16 spi0_RxCounter;
extern volatile UWord16 spi0_TxCounter;


/***********************************************************************
* SPI init
***********************************************************************/
#define ioctlSPI_INIT(pSpiBase,param) spiInit((arch_sSPI*)pSpiBase)

/***********************************************************************
* SPI control command macros
***********************************************************************/

/* SPI peripheral enable/disable */
#define ioctlSPI_DEVICE(pSpiBase,param) \
 if (param) periphBitSet(SPI_SPE, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg ); \
 else periphBitClear(SPI_SPE, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )

/* SPI MASTER/SLAVE mode set */
#define ioctlSPI_SET_MODE(pSpiBase,param) \
 if (param) periphBitSet(SPI_SPMSTR, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg ); \
 else periphBitClear(SPI_SPMSTR, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )

/* SPI data shift order set */
#define ioctlSPI_SET_ORDER(pSpiBase,param) \
 if (param) periphBitSet(SPI_DSO, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg ); \
 else periphBitClear(SPI_DSO, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )
 
/* SPI clock polarity set */
#define ioctlSPI_SET_CLOCK_POLARITY(pSpiBase,param) \
 if (param) periphBitSet(SPI_CPOL, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg ); \
 else periphBitClear(SPI_CPOL, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )

/* SPI clock phase set */
#define ioctlSPI_SET_CLOCK_PHASE(pSpiBase,param) \
 if (param) periphBitSet(SPI_CPHA, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg ); \
 else periphBitClear(SPI_CPHA, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )

/* SPI mode fault detect set */
#define ioctlSPI_SET_MODE_FAULT(pSpiBase,param) \
 if (param) periphBitSet(SPI_MODFEN, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg ); \
 else periphBitClear(SPI_MODFEN, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )

/* SPI receive interrupt enable/disable */
#define ioctlSPI_RX_FULL_INT(pSpiBase,param) \
 if (param) periphBitSet(SPI_SPRIE, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg ); \
 else periphBitClear(SPI_SPRIE, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )

/* SPI transmit interrupt enable/disable */
#define ioctlSPI_TX_EMPTY_INT(pSpiBase,param) \
 if (param) periphBitSet(SPI_SPTIE, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg ); \
 else periphBitClear(SPI_SPTIE, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )

/* SPI transmit interrupt enable/disable */
#define ioctlSPI_ERROR_INT(pSpiBase,param) \
 if (param) periphBitSet(SPI_ERRIE, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg ); \
 else periphBitClear(SPI_ERRIE, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )

/* set data size register */
#define ioctlSPI_SET_DATA_SIZE(pSpiBase,param) periphMemWrite( ((UWord16) (param) - 1) & 0x000F, \
                                          (UWord16 *) &((arch_sSPI*)pSpiBase)->DataSizeReg )
/* write to [7:6] bits in SPSCR - sets SPI baud divisor */
#define ioctlSPI_SET_BAUD_DIV(pSpiBase,param) {periphBitClear(0x00C0, \
                           (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg );\
                           periphBitSet( ((UWord16) (param)) & 0x00C0, \
                           (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg );}
/* write SPI Tx register */
#define ioctlSPI_WRITE(pSpiBase,param) periphMemWrite((UWord16) (param), \
                                       (UWord16 *) &((arch_sSPI*)pSpiBase)->DataTxReg )
/* reads SPI Rx register */
#define ioctlSPI_READ(pSpiBase,param) periphMemRead( \
                                      (UWord16 *) &((arch_sSPI*)pSpiBase)->DataRxReg )

/* test SPI Tx reg. empty bit */
#define ioctlSPI_GET_TX_EMPTY(pSpiBase,param) periphBitTest(SPI_SPTE, \
                                     (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )

/* test SPI Rx reg. full bit */
#define ioctlSPI_GET_RX_FULL(pSpiBase,param) periphBitTest(SPI_SPRF, \
                                     (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )

/* test SPI overflow bit */
#define ioctlSPI_GET_RX_OVERFLOW(pSpiBase,param) periphBitTest(SPI_OVRF, \
                                     (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )
/* test SPI mode fault occurence bit */
#define ioctlSPI_GET_MODE_FAULT(pSpiBase,param) periphBitTest(SPI_MODF, \
                                     (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )

/* test SPI mode fault occurence bit */
#define ioctlSPI_GET_ERROR(pSpiBase,param) periphBitTest(SPI_MODF | SPI_OVRF, \
                                     (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )


/* clear SPI mode fault occurence bit - cleared by writing "1" to MODF */
#define ioctlSPI_CLEAR_MODE_FAULT(pSpiBase,param) periphBitSet(SPI_MODF, \
                                     (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )
                   
/* ??? clear SPI overflow bit (OVRF) - by reading status control register */
#define ioctlSPI_CLEAR_RX_OVERFLOW(pSpiBase,param) \
                       periphMemRead((UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg )



/***********************************************************************
*
* SPI_CLEAR_EXCEPTION
*
***********************************************************************/

#define ioctlSPI_CLEAR_EXCEPTION(pSpiBase,param)  \
         periphBitClear(SPI_STATUS_EXCEPTION_EXIST | SPI_EXCEPTION_BUFFER_OVERFLOW |\
          SPI_EXCEPTION_OVERRUN | SPI_EXCEPTION_MODE_FAULT, &spi0_status)

/***********************************************************************
*
* SPI_GET_STATUS
*
***********************************************************************/

#define ioctlSPI_GET_STATUS(pSpiBase,param)  \
	         periphMemRead(&spi0_status)

/***********************************************************************
*
* SPI_WRITE_CANCEL
*
***********************************************************************/

#define ioctlSPI_WRITE_CANCEL(pSpiBase,param)  \
	     {periphBitClear(SPI_SPTIE, (UWord16 *) &((arch_sSPI*)pSpiBase)->ControlReg); \
	      periphMemWrite(0x0000, &spi0_TxCounter); \
	      periphBitClear(SPI_STATUS_WRITE_INPROGRESS, &spi0_status);}
	      
/***********************************************************************
*
* SPI_READ_CANCEL
*
***********************************************************************/

#define ioctlSPI_READ_CANCEL(pSpiBase,param)  \
	      {periphMemWrite(0x0000, &spi0_RxCounter); \
	       periphBitClear(SPI_STATUS_READ_INPROGRESS, &spi0_status);} 


/****************************************************************************
* Configuration items for appconfig.h (init values, ...),
* should be copied to AppConfig.h
* When item is #undef then is not initialized
*****************************************************************************/

/* SPI0 Status Control Reg (SPSCR) */
/* #define SPI0_STATUS_CONTROL_REG	0 */
/* SPI0 Data Size Reg (SPDSR) num=(num_bits-1) */
/* #define SPI0_DATA_SIZE_REG		0x000F */


#endif
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