adc.c

来自「MC56F802BLDC 可以使用的算法 就是电机启动有点慢」· C语言 代码 · 共 251 行

/*****************************************************************************
*
* Motorola Inc.
* (c) Copyright 2001 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
******************************************************************************
*
* File Name: adc.c
*
* Description: ADC driver
*
* Modules Included:
*
*****************************************************************************/

#include "types.h"
#include "arch.h"
#include "periph.h"

#include "appconfig.h"
#include "adc.h"

/* initialization of ADC A or B module */
/* - it is called through ioctl(ADC_x, ADC_INIT, 0) */
void adcInit(arch_sADC *pAdcBase)
{

 if (pAdcBase==ADC_A)
  {
   /* init of ADC A module */
 #ifdef ADC_A_CHANNEL_LIST_REG1
  periphMemWrite(ADC_A_CHANNEL_LIST_REG1, &pAdcBase->ChannelList1Reg);
 #endif
 #ifdef ADC_A_CHANNEL_LIST_REG2
  periphMemWrite(ADC_A_CHANNEL_LIST_REG2, &pAdcBase->ChannelList2Reg);
 #endif
 #ifdef ADC_A_SAMPLE_DISABLE_REG
  periphMemWrite(ADC_A_SAMPLE_DISABLE_REG, &pAdcBase->DisableReg);
 #endif
 /* status registers are not initialized */
 /* result registers are not initialized */
 
 /* low limit registers */
 #ifdef ADC_A_LOW_LIMIT_REG0
  periphMemWrite(ADC_A_LOW_LIMIT_REG0, &pAdcBase->LowLimitReg[0]);
 #endif
 #ifdef ADC_A_LOW_LIMIT_REG1
  periphMemWrite(ADC_A_LOW_LIMIT_REG1, &pAdcBase->LowLimitReg[1]);
 #endif
 #ifdef ADC_A_LOW_LIMIT_REG2
  periphMemWrite(ADC_A_LOW_LIMIT_REG2, &pAdcBase->LowLimitReg[2]);
 #endif
 #ifdef ADC_A_LOW_LIMIT_REG3
  periphMemWrite(ADC_A_LOW_LIMIT_REG3, &pAdcBase->LowLimitReg[3]);
 #endif
 #ifdef ADC_A_LOW_LIMIT_REG4
  periphMemWrite(ADC_A_LOW_LIMIT_REG4, &pAdcBase->LowLimitReg[4]);
 #endif
 #ifdef ADC_A_LOW_LIMIT_REG5
  periphMemWrite(ADC_A_LOW_LIMIT_REG5, &pAdcBase->LowLimitReg[5]);
 #endif
 #ifdef ADC_A_LOW_LIMIT_REG6
  periphMemWrite(ADC_A_LOW_LIMIT_REG6, &pAdcBase->LowLimitReg[6]);
 #endif
 #ifdef ADC_A_LOW_LIMIT_REG7
  periphMemWrite(ADC_A_LOW_LIMIT_REG7, &pAdcBase->LowLimitReg[7]);
 #endif
 /* high limit registers */
 #ifdef ADC_A_HIGH_LIMIT_REG0
  periphMemWrite(ADC_A_HIGH_LIMIT_REG0, &pAdcBase->HighLimitReg[0]);
 #endif
 #ifdef ADC_A_HIGH_LIMIT_REG1
  periphMemWrite(ADC_A_HIGH_LIMIT_REG1, &pAdcBase->HighLimitReg[1]);
 #endif
  #ifdef ADC_A_HIGH_LIMIT_REG2
  periphMemWrite(ADC_A_HIGH_LIMIT_REG2, &pAdcBase->HighLimitReg[2]);
 #endif
 #ifdef ADC_A_HIGH_LIMIT_REG3
  periphMemWrite(ADC_A_HIGH_LIMIT_REG3, &pAdcBase->HighLimitReg[3]);
 #endif
 #ifdef ADC_A_HIGH_LIMIT_REG4
  periphMemWrite(ADC_A_HIGH_LIMIT_REG4, &pAdcBase->HighLimitReg[4]);
 #endif
 #ifdef ADC_A_HIGH_LIMIT_REG5
  periphMemWrite(ADC_A_HIGH_LIMIT_REG5, &pAdcBase->HighLimitReg[5]);
 #endif
 #ifdef ADC_A_HIGH_LIMIT_REG6
  periphMemWrite(ADC_A_HIGH_LIMIT_REG6, &pAdcBase->HighLimitReg[6]);
 #endif
 #ifdef ADC_A_HIGH_LIMIT_REG7
  periphMemWrite(ADC_A_HIGH_LIMIT_REG7, &pAdcBase->HighLimitReg[7]);
 #endif
 /* offset registers */
 #ifdef ADC_A_OFFSET_REG0
  periphMemWrite(ADC_A_OFFSET_REG0, &pAdcBase->OffsetReg[0]);
 #endif
 #ifdef ADC_A_OFFSET_REG1
  periphMemWrite(ADC_A_OFFSET_REG1, &pAdcBase->OffsetReg[1]);
 #endif
 #ifdef ADC_A_OFFSET_REG2
  periphMemWrite(ADC_A_OFFSET_REG2, &pAdcBase->OffsetReg[2]);
 #endif
 #ifdef ADC_A_OFFSET_REG3
  periphMemWrite(ADC_A_OFFSET_REG3, &pAdcBase->OffsetReg[3]);
 #endif 
 #ifdef ADC_A_OFFSET_REG4
  periphMemWrite(ADC_A_OFFSET_REG4, &pAdcBase->OffsetReg[4]);
 #endif	
 #ifdef ADC_A_OFFSET_REG5
  periphMemWrite(ADC_A_OFFSET_REG5, &pAdcBase->OffsetReg[5]);
 #endif
 #ifdef ADC_A_OFFSET_REG6
  periphMemWrite(ADC_A_OFFSET_REG6, &pAdcBase->OffsetReg[6]);
 #endif
 #ifdef ADC_A_OFFSET_REG7
  periphMemWrite(ADC_A_OFFSET_REG7, &pAdcBase->OffsetReg[7]);
 #endif
 
 /* control registers, initialized last after all initialization */
 #ifdef ADC_A_ZERO_CROSS_CONTROL_REG
  periphMemWrite(ADC_A_ZERO_CROSS_CONTROL_REG, &pAdcBase->ZeroCrossControlReg);
 #endif
 #ifdef ADC_A_CONTROL_REG2
  periphMemWrite(ADC_A_CONTROL_REG2, &pAdcBase->Control2Reg);
 #endif
 #ifdef ADC_A_CONTROL_REG1
  periphMemWrite(ADC_A_CONTROL_REG1, &pAdcBase->Control1Reg);
 #endif

  }
 else
  {
   /* init of ADC B module */
 #ifdef ADC_B_CHANNEL_LIST_REG1
  periphMemWrite(ADC_B_CHANNEL_LIST_REG1, &pAdcBase->ChannelList1Reg);
 #endif
 #ifdef ADC_B_CHANNEL_LIST_REG2
  periphMemWrite(ADC_B_CHANNEL_LIST_REG2, &pAdcBase->ChannelList2Reg);
 #endif
 #ifdef ADC_B_SAMPLE_DISABLE_REG
  periphMemWrite(ADC_B_SAMPLE_DISABLE_REG, &pAdcBase->DisableReg);
 #endif
 /* status registers are not initialized */
 /* result registers are not initialized */
 
 /* low limit registers */
 #ifdef ADC_B_LOW_LIMIT_REG0
  periphMemWrite(ADC_B_LOW_LIMIT_REG0, &pAdcBase->LowLimitReg[0]);
 #endif
 #ifdef ADC_B_LOW_LIMIT_REG1
  periphMemWrite(ADC_B_LOW_LIMIT_REG1, &pAdcBase->LowLimitReg[1]);
 #endif
 #ifdef ADC_B_LOW_LIMIT_REG2
  periphMemWrite(ADC_B_LOW_LIMIT_REG2, &pAdcBase->LowLimitReg[2]);
 #endif
 #ifdef ADC_B_LOW_LIMIT_REG3
  periphMemWrite(ADC_B_LOW_LIMIT_REG3, &pAdcBase->LowLimitReg[3]);
 #endif
 #ifdef ADC_B_LOW_LIMIT_REG4
  periphMemWrite(ADC_B_LOW_LIMIT_REG4, &pAdcBase->LowLimitReg[4]);
 #endif
 #ifdef ADC_B_LOW_LIMIT_REG5
  periphMemWrite(ADC_B_LOW_LIMIT_REG5, &pAdcBase->LowLimitReg[5]);
 #endif
 #ifdef ADC_B_LOW_LIMIT_REG6
  periphMemWrite(ADC_B_LOW_LIMIT_REG6, &pAdcBase->LowLimitReg[6]);
 #endif
 #ifdef ADC_B_LOW_LIMIT_REG7
  periphMemWrite(ADC_B_LOW_LIMIT_REG7, &pAdcBase->LowLimitReg[7]);
 #endif
 /* high limit registers */
 #ifdef ADC_B_HIGH_LIMIT_REG0
  periphMemWrite(ADC_B_HIGH_LIMIT_REG0, &pAdcBase->HighLimitReg[0]);
 #endif
 #ifdef ADC_B_HIGH_LIMIT_REG1
  periphMemWrite(ADC_B_HIGH_LIMIT_REG1, &pAdcBase->HighLimitReg[1]);
 #endif
  #ifdef ADC_B_HIGH_LIMIT_REG2
  periphMemWrite(ADC_B_HIGH_LIMIT_REG2, &pAdcBase->HighLimitReg[2]);
 #endif
 #ifdef ADC_B_HIGH_LIMIT_REG3
  periphMemWrite(ADC_B_HIGH_LIMIT_REG3, &pAdcBase->HighLimitReg[3]);
 #endif
 #ifdef ADC_B_HIGH_LIMIT_REG4
  periphMemWrite(ADC_B_HIGH_LIMIT_REG4, &pAdcBase->HighLimitReg[4]);
 #endif
 #ifdef ADC_B_HIGH_LIMIT_REG5
  periphMemWrite(ADC_B_HIGH_LIMIT_REG5, &pAdcBase->HighLimitReg[5]);
 #endif
 #ifdef ADC_B_HIGH_LIMIT_REG6
  periphMemWrite(ADC_B_HIGH_LIMIT_REG6, &pAdcBase->HighLimitReg[6]);
 #endif
 #ifdef ADC_B_HIGH_LIMIT_REG7
  periphMemWrite(ADC_B_HIGH_LIMIT_REG7, &pAdcBase->HighLimitReg[7]);
 #endif
 /* offset registers */
 #ifdef ADC_B_OFFSET_REG0
  periphMemWrite(ADC_B_OFFSET_REG0, &pAdcBase->OffsetReg[0]);
 #endif
 #ifdef ADC_B_OFFSET_REG1
  periphMemWrite(ADC_B_OFFSET_REG1, &pAdcBase->OffsetReg[1]);
 #endif
 #ifdef ADC_B_OFFSET_REG2
  periphMemWrite(ADC_B_OFFSET_REG2, &pAdcBase->OffsetReg[2]);
 #endif
 #ifdef ADC_B_OFFSET_REG3
  periphMemWrite(ADC_B_OFFSET_REG3, &pAdcBase->OffsetReg[3]);
 #endif 
 #ifdef ADC_B_OFFSET_REG4
  periphMemWrite(ADC_B_OFFSET_REG4, &pAdcBase->OffsetReg[4]);
 #endif	
 #ifdef ADC_B_OFFSET_REG5
  periphMemWrite(ADC_B_OFFSET_REG5, &pAdcBase->OffsetReg[5]);
 #endif
 #ifdef ADC_B_OFFSET_REG6
  periphMemWrite(ADC_B_OFFSET_REG6, &pAdcBase->OffsetReg[6]);
 #endif
 #ifdef ADC_B_OFFSET_REG7
  periphMemWrite(ADC_B_OFFSET_REG7, &pAdcBase->OffsetReg[7]);
 #endif

 /* control registers, initialized last after all initialization */
 #ifdef ADC_B_ZERO_CROSS_CONTROL_REG
  periphMemWrite(ADC_B_ZERO_CROSS_CONTROL_REG, &pAdcBase->ZeroCrossControlReg);
 #endif
 #ifdef ADC_B_CONTROL_REG2
  periphMemWrite(ADC_B_CONTROL_REG2, &pAdcBase->Control2Reg);
 #endif
 #ifdef ADC_B_CONTROL_REG1
  periphMemWrite(ADC_B_CONTROL_REG1, &pAdcBase->Control1Reg);
 #endif


  }
}



/* reads all 8 results from result registers to array (adc_tBuff) */
void AdcRdResults(adc_tBuff buff, UWord16 *reg)
{
 UWord16 i;
 // pridat cykl cteni
 for (i=0; i<8; i++)
  {
   buff[i] = periphMemRead(reg++);
  }
}