sci.h

MC56F802BLDC 可以使用的算法 就是电机启动有点慢

#define ioctlSCI_RECEIVER(pSciBase, param)		\
     if (param == SCI_ENABLE) periphBitSet (SCI_RE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
     else                     periphBitClear (SCI_RE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

#define ioctlSCI_WAKEUP_CONDITION(pSciBase, param)		\
     if  (param == SCI_WAKE_BY_ADDRESS) periphBitSet (SCI_WAKE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
     else                               periphBitClear (SCI_WAKE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

#define ioctlSCI_DATA_FORMAT(pSciBase, param)		\
     if   (param == SCI_WORD_9BIT) periphBitSet (SCI_M,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
     else                          periphBitClear (SCI_M,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

#define ioctlSCI_PARITY(pSciBase, param)		\
     if      (param == SCI_PARITY_ODD)  periphBitSet ((SCI_PE | SCI_PT),(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
     else if (param == SCI_PARITY_EVEN) {periphBitSet (SCI_PE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
			                             periphBitClear(SCI_PT,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg));} \
     else                                periphBitClear (SCI_PE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

#define ioctlSCI_DATA_POLARITY(pSciBase, param)		\
     if (param == SCI_INVERTED) periphBitSet (SCI_POL,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
     else                       periphBitClear (SCI_POL,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

#define ioctlSCI_MODULE_IN_WAIT(pSciBase, param)		\
     if (param == SCI_DISABLE) periphBitSet (SCI_SWAI,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
     else                      periphBitClear (SCI_SWAI,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

/* ??????????????????????????????????????????????????????????????????????? */
#define ioctlSCI_SEND_BREAK(pSciBase, param)		\
			periphBitSet (SCI_SBK,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
			 periphBitClear (SCI_SBK,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

#define ioctlSCI_WAIT(pSciBase, param)		\
			periphBitSet (SCI_RWU,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))				

#define ioctlSCI_WAKEUP(pSciBase, param)		\
			periphBitClear (SCI_RWU,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))				
/* ??????????????????????????????????????????????????????????????????????? */

#define ioctlSCI_TX_EMPTY_INT(pSciBase, param)		\
     if (param == SCI_ENABLE) periphBitSet (SCI_TEIE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
     else                     periphBitClear (SCI_TEIE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

#define ioctlSCI_TX_IDLE_INT(pSciBase, param)		\
     if (param == SCI_ENABLE) periphBitSet (SCI_TIIE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
     else                     periphBitClear (SCI_TIIE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

#define ioctlSCI_RX_FULL_INT(pSciBase, param)		\
     if (param == SCI_ENABLE) periphBitSet (SCI_RIE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
     else                     periphBitClear (SCI_RIE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

#define ioctlSCI_RX_ERROR_INT(pSciBase, param)		\
     if (param == SCI_ENABLE) periphBitSet (SCI_REIE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
     else                     periphBitClear (SCI_REIE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

#define ioctlSCI_READ_CONTROL_REG(pSciBase, param)		\
        periphMemRead ((UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

#define ioctlSCI_WRITE_CONTROL_REG(pSciBase, param)		\
        periphMemWrite (param,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

/***********************************************************************
*
* SCI Status Register
*
***********************************************************************/

#define ioctlSCI_GET_STATUS_REG(pSciBase,param)  \
             periphMemRead((UWord16*)(&((arch_sSCI*)pSciBase)->StatusReg))

#define ioctlSCI_CLEAR_STATUS_REG(pSciBase,param)  \
             periphMemWrite(0x0000,(UWord16*)(&((arch_sSCI*)pSciBase)->StatusReg))

#define ioctlSCI_GET_TX_EMPTY(pSciBase,param)  \
             periphBitTest(SCI_TDRE, (UWord16*)(&((arch_sSCI*)pSciBase)->StatusReg))

#define ioctlSCI_GET_TX_IDLE(pSciBase,param)  \
             periphBitTest(SCI_TIDLE, (UWord16*)(&((arch_sSCI*)pSciBase)->StatusReg))

#define ioctlSCI_GET_RX_FULL(pSciBase,param)  \
             periphBitTest(SCI_RDRF, (UWord16*)(&((arch_sSCI*)pSciBase)->StatusReg))

#define ioctlSCI_GET_RX_IDLE(pSciBase,param)  \
             periphBitTest(SCI_RIDLE, (UWord16*)(&((arch_sSCI*)pSciBase)->StatusReg))

#define ioctlSCI_GET_ERROR(pSciBase,param)  \
             periphBitTest((SCI_OR | SCI_NF | SCI_FE | SCI_PF), (UWord16*)(&((arch_sSCI*)pSciBase)->StatusReg))

#define ioctlSCI_GET_RX_OVERRUN(pSciBase,param)  \
             periphBitTest(SCI_OR, (UWord16*)(&((arch_sSCI*)pSciBase)->StatusReg))

#define ioctlSCI_GET_RX_NOISE_ERROR(pSciBase,param)  \
             periphBitTest(SCI_NF, (UWord16*)(&((arch_sSCI*)pSciBase)->StatusReg))

#define ioctlSCI_GET_RX_FRAMING_ERROR(pSciBase,param)  \
             periphBitTest(SCI_FE, (UWord16*)(&((arch_sSCI*)pSciBase)->StatusReg))
             
#define ioctlSCI_GET_RX_PARITY_ERROR(pSciBase,param)  \
             periphBitTest(SCI_PF, (UWord16*)(&((arch_sSCI*)pSciBase)->StatusReg))

#define ioctlSCI_GET_RX_ACTIVE(pSciBase,param)  \
             periphBitTest(SCI_RAF, (UWord16*)(&((arch_sSCI*)pSciBase)->StatusReg))

/***********************************************************************             
*
* SCI Data Register
*
***********************************************************************/

#define ioctlSCI_READ_DATA(pSciBase,param)    \
             periphMemRead((UWord16*)(&((arch_sSCI*)pSciBase)->DataReg))

#define ioctlSCI_WRITE_DATA(pSciBase,param)    \
             periphMemWrite(param, (UWord16*)(&((arch_sSCI*)pSciBase)->DataReg))

/***********************************************************************
*
* SCI_CLEAR_EXCEPTION
*
***********************************************************************/

#define ioctlSCI_CLEAR_EXCEPTION(pSciBase,param)  \
        if (pSciBase == SCI_0) periphBitClear(SCI_STATUS_EXCEPTION_EXIST | SCI_EXCEPTION_BUFFER_OVERFLOW, &sci0_status);  \
        else                  periphBitClear(SCI_STATUS_EXCEPTION_EXIST | SCI_EXCEPTION_BUFFER_OVERFLOW, &sci1_status)

/***********************************************************************
*
* SCI_GET_STATUS
*
***********************************************************************/

#define ioctlSCI0_GET_STATUS(pSciBase,param)  \
	         periphMemRead(&sci0_status)

#define ioctlSCI1_GET_STATUS(pSciBase,param)  \
	         periphMemRead(&sci1_status)

/***********************************************************************
*
* SCI_WRITE_CANCEL
*
***********************************************************************/

#define ioctlSCI_WRITE_CANCEL(pSciBase,param)  \
	    if (pSciBase == SCI_0){periphMemWrite(0x0000, &sci0_TxCounter); \
	                           periphBitClear(SCI_STATUS_WRITE_INPROGRESS, &sci0_status); \
                               periphBitClear (SCI_TEIE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg));} \
	    else                 { periphMemWrite(0x0000, &sci1_TxCounter); \
	                           periphBitClear(SCI_STATUS_WRITE_INPROGRESS, &sci1_status); \
                               periphBitClear (SCI_TEIE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg));}

/*
alternative solution for time critical implementation:
#define ioctlSCI_WRITE_CANCEL(pSciBase,param) ioctlSCI_WRITE_CANCEL_##param##(pSciBase)

#define ioctlSCI_WRITE_CANCEL_SCI0(pSciBase) \
        periphMemWrite(0x0000, &sci0_TxCounter); \
	    periphBitClear(SCI_STATUS_WRITE_INPROGRESS, &sci0_status);
	    
#define ioctlSCI_WRITE_CANCEL_SCI1(pSciBase) \
        periphMemWrite(0x0000, &sci1_TxCounter); \
	    periphBitClear(SCI_STATUS_WRITE_INPROGRESS, &sci1_status);
*/
/***********************************************************************
*
* SCI_READ_CANCEL
*
***********************************************************************/

#define ioctlSCI_READ_CANCEL(pSciBase,param)  \
	    if (pSciBase == SCI_0){ periphMemWrite(0x0000, &sci0_RxCounter); \
	                           periphBitClear(SCI_STATUS_READ_INPROGRESS, &sci0_status);} \
	    else                 { periphMemWrite(0x0000, &sci1_RxCounter); \
	                           periphBitClear(SCI_STATUS_READ_INPROGRESS, &sci1_status);}
/*
alternative solution for time critical implementation:
#define ioctlSCI_READ_CANCEL(pSciBase,param)  ioctlSCI_READ_CANCEL_##param##(pSciBase)

#define ioctlSCI_READ_CANCEL_SCI0(pSciBase) \
        periphMemWrite(0x0000, &sci0_RxCounter); \
        periphBitClear(SCI_STATUS_READ_INPROGRESS, &sci0_status);

#define ioctlSCI_READ_CANCEL_SCI1(pSciBase) \
        periphMemWrite(0x0000, &sci1_RxCounter); \
        periphBitClear(SCI_STATUS_READ_INPROGRESS, &sci1_status)
*/	                           
/***********************************************************************
*
* SCI prototypes (implemented in sci.c)
*
***********************************************************************/

void read_SCI_0_NON_BLOCKING(UWord16 *data, UWord16 size);
void read_SCI_0_BLOCKING(UWord16 *data, UWord16 size);

void write_SCI_0_NON_BLOCKING(UWord16 *data, UWord16 size);
void write_SCI_0_BLOCKING(UWord16 *data, UWord16 size);

void read_SCI_1_NON_BLOCKING(UWord16 *data, UWord16 size);
void read_SCI_1_BLOCKING(UWord16 *data, UWord16 size);

void write_SCI_1_NON_BLOCKING(UWord16 *data, UWord16 size);
void write_SCI_1_BLOCKING(UWord16 *data, UWord16 size);

void Sci0RxFullISR(void);
void Sci0TxEmptyISR(void);
void Sci0RxErrorISR(void);

void Sci1RxFullISR(void);
void Sci1TxEmptyISR(void);
void Sci1RxErrorISR(void);

/**********************************************************************
*
* Include of device specific SCI commands and defines
*
***********************************************************************/

#include "scitarget.h"  /* device specific defines */

#endif