sci.h

MC56F802BLDC 可以使用的算法 就是电机启动有点慢

/******************************************************************************
*
* Motorola Inc.
* (c) Copyright 2001 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
*******************************************************************************
*
* FILE NAME: sci.h
*
* DESCRIPTION: Header file for SCI driver
*
* MODULES INCLUDED: none
*
* NOTES:
*
*******************************************************************************/

#ifndef __SCI_H
#define __SCI_H

/************************************************************
* SCI module identifiers, correspond to module base address
*************************************************************/

#define SCI_0	(&ArchIO.Sci0)
#define SCI_1	(&ArchIO.Sci1)

/****************************************************
* Configurable items, i.e. defines, for appconfig.h
*****************************************************

  void scixRxFullISR( void );         prototype for user ISR 
  #define INTERRUPT_VECTOR_ADDR_yy    scixRxFullISR
  #define ITCN_INTERRUPT_PRIORITY_yy  value 0-7 (0 = interrupt disabled)


  #define  SCI_x_BAUD_RATE_REG        0x0000
  #define  SCI_x_CONTROL_REG          0x0000

  where:
         x  is SCI module (0 or 1)
         yy  is interrupt vector number
                53 - SCI 0 Receiver Full
                52 - SCI 0 Receiver Error
                51 - SCI 0 Transmitter Ready
                50 - SCI 0 Transmitter Complete
                49 - SCI 1 Receiver Full
                48 - SCI 1 Receiver Error
                47 - SCI 1 Transmitter Ready
                46 - SCI 1 Transmitter Complete                                           
*/

/*****************************************************************
* ioctl() commands
*
*  Word16 ioctl( PWM_module_identifier, Command_name, Parameter );
*
******************************************************************

 COMMAND NAME                      PARAMETERS, COMMENTS
--------------------------------------------------------*/

#define SCI_INIT                 /* NULL */
#define SCI_SET_BAUDRATE_DIV     /* UWord16 */
#define SCI_LOOP_MODE            /* SCI_LOOP_ENABLE / SCI_LOOP_DISABLE / SCI_LOOP_SINGLE_WIRE */
#define SCI_TRANSMITTER          /* SCI_ENABLE / SCI_DISABLE */
#define SCI_RECEIVER             /* SCI_ENABLE / SCI_DISABLE */
#define SCI_WAKEUP_CONDITION     /* SCI_WAKE_BY_ADDRESS / SCI_WAKE_BY_IDLE */
#define SCI_DATA_FORMAT          /* SCI_WORD_9BIT / SCI_WORD_8BIT */
#define SCI_PARITY               /* SCI_PARITY_ODD / SCI_PARITY_EVEN / SCI_PARITY_NONE */
#define SCI_DATA_POLARITY        /* SCI_INVERTED / SCI_NOT_INVERTED */
#define SCI_MODULE_IN_WAIT       /* SCI_ENABLE / SCI_DISABLE */
#define SCI_SEND_BREAK           /* NULL */
#define SCI_WAIT                 /* NULL */
#define SCI_WAKEUP               /* NULL */
#define SCI_TX_EMPTY_INT         /* SCI_ENABLE / SCI_DISABLE */
#define SCI_TX_IDLE_INT          /* SCI_ENABLE / SCI_DISABLE */
#define SCI_RX_FULL_INT          /* SCI_ENABLE / SCI_DISABLE */
#define SCI_RX_ERROR_INT         /* SCI_ENABLE / SCI_DISABLE */
#define SCI_GET_STATUS_REG       /* NULL */
#define SCI_CLEAR_STATUS_REG     /* NULL */
#define SCI_READ_DATA            /* NULL */
#define SCI_WRITE_DATA           /* UWord16 */
#define SCI_READ_CONTROL_REG     /* NULL */
#define SCI_WRITE_CONTROL_REG    /* UWord16 */
#define SCI_GET_TX_EMPTY         /* NULL */
#define SCI_GET_TX_IDLE          /* NULL */
#define SCI_GET_RX_FULL          /* NULL */
#define SCI_GET_RX_IDLE          /* NULL */
#define SCI_GET_ERROR            /* NULL */
#define SCI_GET_RX_OVERRUN       /* NULL */
#define SCI_GET_RX_NOISE_ERROR   /* NULL */
#define SCI_GET_RX_FRAMING_ERROR /* NULL */
#define SCI_GET_RX_PARITY_ERROR  /* NULL */
#define SCI_GET_RX_ACTIVE        /* NULL */
/* high-level ioctl commands */
#define SCI0_GET_STATUS          /* NULL */
#define SCI1_GET_STATUS          /* NULL */
#define SCI_CLEAR_EXCEPTION      /* NULL */
#define SCI_WRITE_CANCEL         /* NULL */
#define SCI_READ_CANCEL          /* NULL */

/****************************************************************************
* SCI constants use in the ioctl functions
*****************************************************************************/

#define BLOCKING          1      /* blocking mode for read/write functions */
#define NON_BLOCKING      2      /* non-blocking mode for read/write functions */

/* SCI baud rates only for DSP core at 80MHz */
#define SCI_BAUD_230400          11
#define SCI_BAUD_115200          22
#define SCI_BAUD_76800           33
#define SCI_BAUD_57600           43         
#define SCI_BAUD_38400           65
#define SCI_BAUD_28800           87
#define SCI_BAUD_19200           130
#define SCI_BAUD_14400           174
#define SCI_BAUD_9600            260
#define SCI_BAUD_7200            347
#define SCI_BAUD_4800            521
#define SCI_BAUD_2400            1042
#define SCI_BAUD_1200            2083
#define SCI_BAUD_600             4167

/* command parameters */
#define SCI_PARITY_NONE          1   /* parity disabled */
#define SCI_PARITY_ODD           2   /* odd parity */
#define SCI_PARITY_EVEN          3   /* even parity */
#define SCI_WORD_9BIT            4   /* startbit, nine data bits, stop bit */
#define SCI_WORD_8BIT            5   /* startbit, eight data bits, stop bit */
#define SCI_WAKE_BY_ADDRESS      6   /* address mark wakeup */
#define SCI_WAKE_BY_IDLE         7   /* idle line wakeup */
#define SCI_ENABLE               8   /* no loop mode */
#define SCI_DISABLE              9   /* loop mode with internal TXD feedback to RXD */
#define SCI_LOOP_ENABLE          10  /* enable loop mode */
#define SCI_LOOP_DISABLE         11  /* disable loop mode */
#define SCI_LOOP_SINGLE_WIRE     12  /* loop mode with internal TXD feedback to RXD */
#define SCI_INVERTED             13  /* inverted transmit and receive data bits */
#define SCI_NOT_INVERTED         14  /* not inverted transmit and receive data bits */

/*****************************************************************
* SCI Register Bits Defines, used in ioct command implementation
******************************************************************/

/* SCI Control Register bits */
#define SCI_LOOP        0x8000
#define SCI_SWAI        0x4000
#define SCI_RSRC        0x2000
#define SCI_M           0x1000
#define SCI_WAKE        0x0800
#define SCI_POL         0x0400
#define SCI_PE          0x0200
#define SCI_PT          0x0100
#define SCI_TEIE        0x0080
#define SCI_TIIE        0x0040
#define SCI_RIE         0x0020
#define SCI_REIE        0x0010
#define SCI_TE          0x0008
#define SCI_RE          0x0004
#define SCI_RWU         0x0002
#define SCI_SBK         0x0001

/* SCI Status registers bits */
#define SCI_TDRE        0x8000
#define SCI_TIDLE       0x4000
#define SCI_RDRF        0x2000
#define SCI_RIDLE       0x1000
#define SCI_OR          0x0800
#define SCI_NF          0x0400
#define SCI_FE          0x0200
#define SCI_PF          0x0100
#define SCI_RAF         0x0001

/* status generated by read/write functions -> SCI0_GET_STATUS, SCI1_GET_STATUS commands */
#define SCI_STATUS_WRITE_INPROGRESS       0x0010    /* write to SCI is in progress */
#define SCI_STATUS_READ_INPROGRESS        0x0020    /* read from SCI is in progress */
#define SCI_STATUS_EXCEPTION_EXIST        0x0040    /* exception exists - HW exception if only this flag is set
                                                                        - SW exception if other exception flags are set */
#define SCI_EXCEPTION_BUFFER_OVERFLOW     0x0008    /* buffer overflow - some bytes were thrown away */

/***********************************************************************
* status variables for read/wrire functions
***********************************************************************/

extern volatile UWord16 sci0_status;
extern volatile UWord16 sci1_status;
extern volatile UWord16 sci0_RxCounter;
extern volatile UWord16 sci1_RxCounter;
extern volatile UWord16 sci0_TxCounter;
extern volatile UWord16 sci1_TxCounter;

/***********************************************************************
*
* SCI Init
*
***********************************************************************/

#define ioctlSCI_INIT(sciBase,param) sciInit((arch_sSCI *)sciBase)
void sciInit(arch_sSCI *sciBase); /* function prototype - implemented in sci.c */

/***********************************************************************
*
* SCI Baud Rate Register
*
***********************************************************************/

#define ioctlSCI_SET_BAUDRATE_DIV(pSciBase, param) \
            periphMemWrite(param, (UWord16 *)(&((arch_sSCI*)pSciBase)->BaudRateReg))	
            
/***********************************************************************
*
* SCI Control Register
*
***********************************************************************/

#define ioctlSCI_LOOP_MODE(pSciBase, param)		\
     if      (param == SCI_LOOP_ENABLE)    { periphBitSet (SCI_LOOP,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg));            \
                                             periphBitClear (SCI_RSRC,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); }        \
     else if (param == SCI_LOOP_SINGLE_WIRE) periphBitSet (SCI_LOOP | SCI_RSRC,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
     else                                    periphBitClear (SCI_LOOP,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))

#define ioctlSCI_TRANSMITTER(pSciBase, param)		\
     if (param == SCI_ENABLE) periphBitSet (SCI_TE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg)); \
     else                     periphBitClear (SCI_TE,(UWord16 *)(&((arch_sSCI*)pSciBase)->ControlReg))