📄 pwm.h
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#define ioctlPWM_HARDWARE_ACCELERATION(pPwmBase,param) \
if (param) {periphBitSet(PWM_ENHA, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg));} \
else {periphBitClear(PWM_ENHA, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg));}
#define ioctlPWM_SET_CHANNEL_MASK(pPwmBase,param) \
{ periphBitClear(~(((((UWord16)(param)) << 8)) | ((PWM_MAX_INT) & (~(MC_PWM_ALL_SIGNALS << 8 )))), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \
periphBitSet((((UWord16)(param)) << 8), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); }
#define ioctlPWM_SET_LOAD_MODE(pPwmBase,param) \
{ periphBitSet(PWM_ENHA,(UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \
periphBitClear(~(((((UWord16)(param)) << 4)) | ((PWM_MAX_INT) & (~((PWM_LOAD_FROM_0_TO_5 | PWM_LOAD_FROM_0_TO_3) << 4 )))), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \
periphBitSet(PWM_ENHA,(UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \
periphBitSet((((UWord16)(param)) << 4), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); }
// periphBitSet(PWM_ENHA, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \ needed in older PWM rev
#define ioctlPWM_SET_SWAP(pPwmBase,param) \
{ periphBitSet(PWM_ENHA,(UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \
periphBitClear(~((((UWord16)(param))) | ((PWM_MAX_INT) & (~(PWM_CHANNEL_45 | PWM_CHANNEL_23 | PWM_CHANNEL_01)))), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \
periphBitSet(PWM_ENHA,(UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \
periphBitSet(((UWord16)(param)), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); }
// periphBitSet(PWM_ENHA, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \ needed in older PWM rev
/**********************************************************************
*
* PWM Fault Status & Acknowledge Register
*
***********************************************************************/
#define ioctlPWM_READ_FAULT_STATUS_REG(pPwmBase,param) \
periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->FaultStatusReg ))
/**********************************************************************
*
* PWM Counter Register
*
***********************************************************************/
#define ioctlPWM_READ_COUNTER_REG(pPwmBase,param) \
periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterReg ))
/*
#define ioctlPWM_WRITE_COUNTER_REG(pPwmBase,param) \
periphMemWrite(((UWord16)(param)), (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterReg))
*/
/**********************************************************************
*
* PWM Control Register
*
***********************************************************************/
#define ioctlPWM_READ_CONTROL_REG(pPwmBase,param) \
periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg ))
/**********************************************************************
*
* PWM Port Register
*
***********************************************************************/
#define ioctlPWM_READ_PORT_REG(pPwmBase,param) \
periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->PortReg ))
/**********************************************************************
*
* PWM Value Registers
*
***********************************************************************/
#define ioctlPWM_WRITE_VALUE_REG_0(pPwmBase,param) \
periphMemWrite( param , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[0] ))
#define ioctlPWM_WRITE_VALUE_REG_1(pPwmBase,param) \
periphMemWrite( param , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[1] ))
#define ioctlPWM_WRITE_VALUE_REG_2(pPwmBase,param) \
periphMemWrite( param , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[2] ))
#define ioctlPWM_WRITE_VALUE_REG_3(pPwmBase,param) \
periphMemWrite( param , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[3] ))
#define ioctlPWM_WRITE_VALUE_REG_4(pPwmBase,param) \
periphMemWrite( param , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[4] ))
#define ioctlPWM_WRITE_VALUE_REG_5(pPwmBase,param) \
periphMemWrite( param , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[5] ))
#define ioctlPWM_WRITE_VALUE_REGS_COMPL(pPwmBase,param) \
{ periphMemWrite( ((pwm_sComplementaryValues*)param)->pwmChannel_0_Value , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[0])); \
periphMemWrite( ((pwm_sComplementaryValues*)param)->pwmChannel_2_Value , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[2])); \
periphMemWrite( ((pwm_sComplementaryValues*)param)->pwmChannel_4_Value , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[4]));}
#define ioctlPWM_WRITE_VALUE_REGS_INDEP(pPwmBase,param) \
{ periphMemWrite( ((pwm_sIndependentValues*)param)->pwmChannel_0_Value , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[0])); \
periphMemWrite( ((pwm_sIndependentValues*)param)->pwmChannel_1_Value , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[1])); \
periphMemWrite( ((pwm_sIndependentValues*)param)->pwmChannel_2_Value , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[2])); \
periphMemWrite( ((pwm_sIndependentValues*)param)->pwmChannel_3_Value , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[3])); \
periphMemWrite( ((pwm_sIndependentValues*)param)->pwmChannel_4_Value , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[4])); \
periphMemWrite( ((pwm_sIndependentValues*)param)->pwmChannel_5_Value , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[5]));}
#define ioctlPWM_UPDATE_VALUE_REG_0(pPwmBase,param) \
{ UWord16 TempModulus; \
TempModulus = periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterModuloReg )); \
periphMemWrite( mult_r( TempModulus, param ), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[0] )); \
periphBitSet(PWM_LDOK, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); }
#define ioctlPWM_UPDATE_VALUE_REG_1(pPwmBase,param) \
{ UWord16 TempModulus; \
TempModulus = periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterModuloReg )); \
periphMemWrite( mult_r( TempModulus, param ), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[1] )); \
periphBitSet(PWM_LDOK, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); }
#define ioctlPWM_UPDATE_VALUE_REG_2(pPwmBase,param) \
{ UWord16 TempModulus; \
TempModulus = periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterModuloReg )); \
periphMemWrite( mult_r( TempModulus, param ), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[2] )); \
periphBitSet(PWM_LDOK, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); }
#define ioctlPWM_UPDATE_VALUE_REG_3(pPwmBase,param) \
{ UWord16 TempModulus; \
TempModulus = periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterModuloReg )); \
periphMemWrite( mult_r( TempModulus, param ), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[3] )); \
periphBitSet(PWM_LDOK, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); }
#define ioctlPWM_UPDATE_VALUE_REG_4(pPwmBase,param) \
{ UWord16 TempModulus; \
TempModulus = periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterModuloReg )); \
periphMemWrite( mult_r( TempModulus, param ), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[4] )); \
periphBitSet(PWM_LDOK, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); }
#define ioctlPWM_UPDATE_VALUE_REG_5(pPwmBase,param) \
{ UWord16 TempModulus; \
TempModulus = periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterModuloReg )); \
periphMemWrite( mult_r( TempModulus, param ), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[5] )); \
periphBitSet(PWM_LDOK, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); }
#define ioctlPWM_UPDATE_VALUE_REGS_COMPL(pPwmBase,param) \
{ UWord16 TempModulus; \
TempModulus = periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterModuloReg )); \
periphMemWrite( mult_r( TempModulus, ((pwm_sComplementaryValues*)param)->pwmChannel_0_Value) , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[0])); \
periphMemWrite( mult_r( TempModulus, ((pwm_sComplementaryValues*)param)->pwmChannel_2_Value) , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[2])); \
periphMemWrite( mult_r( TempModulus, ((pwm_sComplementaryValues*)param)->pwmChannel_4_Value) , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[4])); \
periphBitSet(PWM_LDOK, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); }
#define ioctlPWM_UPDATE_VALUE_REGS_INDEP(pPwmBase,param) \
{ UWord16 TempModulus; \
TempModulus = periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterModuloReg )); \
periphMemWrite( mult_r( TempModulus, ((pwm_sIndependentValues*)param)->pwmChannel_0_Value) , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[0])); \
periphMemWrite( mult_r( TempModulus, ((pwm_sIndependentValues*)param)->pwmChannel_1_Value) , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[1])); \
periphMemWrite( mult_r( TempModulus, ((pwm_sIndependentValues*)param)->pwmChannel_2_Value) , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[2])); \
periphMemWrite( mult_r( TempModulus, ((pwm_sIndependentValues*)param)->pwmChannel_3_Value) , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[3])); \
periphMemWrite( mult_r( TempModulus, ((pwm_sIndependentValues*)param)->pwmChannel_4_Value) , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[4])); \
periphMemWrite( mult_r( TempModulus, ((pwm_sIndependentValues*)param)->pwmChannel_5_Value) , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[5])); \
periphBitSet(PWM_LDOK, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); }
/**********************************************************************
*
* PWM Output Control Register
*
***********************************************************************/
#define ioctlPWM_SOFTWARE_OUTPUTS_CONTROL(pPwmBase,param) \
{ UWord16 TempOutctl; \
TempOutctl = PWM_PAD_EN | ((pwm_sOutputControl*)param) -> SoftwareControlled << 8 | ((pwm_sOutputControl*)param) -> OutputControl; \
periphMemWrite((TempOutctl), (UWord16 *)(&((arch_sPWM*)pPwmBase)->OutputControlReg)); }
/**********************************************************************
*
* PWM Channel Control Register
*
***********************************************************************/
#define ioctlPWM_SET_MASK_SWAP(pPwmBase,param) \
{ UWord16 TempChannelControl; \
TempChannelControl = (periphMemRead((UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)) & ((PWM_LOAD_FROM_0_TO_5 | PWM_LOAD_FROM_0_TO_3) << 4)); \
TempChannelControl = PWM_ENHA | (((pwm_sChannelControl*)param) -> Mask << 8) | TempChannelControl | ((pwm_sChannelControl*)param) -> Swap; \
periphBitSet(PWM_ENHA, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \
periphMemWrite((TempChannelControl), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); }
// periphBitSet(PWM_ENHA, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \ needed in older PWM rev
/**********************************************************************
*
* PWM_UPDATE_VALUE_SET_VLMODE
*
***********************************************************************/
#define ioctlPWM_UPDATE_VALUE_SET_VLMODE(pPwmBase,param) \
{ UWord16 TempModulus; \
TempModulus = periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterModuloReg ) ); \
periphBitSet(PWM_ENHA, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \
periphBitClear( ((PWM_LOAD_FROM_0_TO_5 | PWM_LOAD_FROM_0_TO_3) << 4), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg) ); \
periphBitSet(PWM_ENHA, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \
periphBitSet( ( (((pwm_sUpdateValueSetVlmode*)param)->Vlmode) << 4 ), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg) ); \
periphMemWrite( mult_r( TempModulus, ((pwm_sUpdateValueSetVlmode*)param)->DutyCycle) , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[0])); \
periphBitSet(PWM_LDOK, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); }
// periphBitSet(PWM_ENHA, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ChannelControlReg)); \ needed in older PWM rev
/**********************************************************************
*
* PWM_CORRECT_DEAD_TIME_COMPL
*
***********************************************************************/
#define ioctlPWM_CORRECT_DEAD_TIME_COMPL(pPwmBase,param) \
{ UWord16 tmp0, tmp1, tmp2, modulo, dead, edge; \
modulo = periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterModuloReg )); \
dead = periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->DeadtimeReg )); \
edge = periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->ConfigReg )) & PWM_EDG; \
if( edge == 0 ) dead = dead >> 1; \
tmp0 = mult_r( modulo, ((pwm_sComplementaryValues*)param)->pwmChannel_0_Value ); \
tmp1 = mult_r( modulo, ((pwm_sComplementaryValues*)param)->pwmChannel_2_Value ); \
tmp2 = mult_r( modulo, ((pwm_sComplementaryValues*)param)->pwmChannel_4_Value ); \
periphMemWrite( tmp0 + dead , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[0])); \
periphMemWrite( tmp0 - dead , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[1])); \
periphMemWrite( tmp1 + dead , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[2])); \
periphMemWrite( tmp1 - dead , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[3])); \
periphMemWrite( tmp2 + dead , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[4])); \
periphMemWrite( tmp2 - dead , (UWord16 *)(&((arch_sPWM*)pPwmBase)->ValueReg[5])); \
periphBitSet(PWM_LDOK, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); }
/**********************************************************************
*
* Include of device specific PWM commands and defines
*
***********************************************************************/
#include "pwmtarget.h" /* device specific defines */
#endif⌨️ 快捷键说明
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