pwm.h

MC56F802BLDC 可以使用的算法 就是电机启动有点慢

							*/    
                             


typedef struct
{
	Word16  pwmChannel_0_Value;
	Word16  pwmChannel_2_Value;
	Word16  pwmChannel_4_Value;
}pwm_sComplementaryValues;

typedef struct
{
	Word16  pwmChannel_0_Value;
	Word16  pwmChannel_1_Value;
	Word16  pwmChannel_2_Value;
	Word16  pwmChannel_3_Value;
	Word16  pwmChannel_4_Value;
	Word16  pwmChannel_5_Value;
}pwm_sIndependentValues;

typedef struct
{
	mc_tPWMSignalMask   SoftwareControlled;
	mc_tPWMSignalMask   OutputControl;
}pwm_sOutputControl;

typedef struct
{
	Word16    DutyCycle;
	UWord16   Vlmode;
}pwm_sUpdateValueSetVlmode;

typedef struct
{
	mc_tPWMSignalMask     Mask;
	pwm_tPWMChannelSwap   Swap;
}pwm_sChannelControl;


/*****************************************************************
* PWM Register Bits Defines, used in ioct command implementation
******************************************************************/

#define PWM_MAX_INT   0xffff

/* PWM Control Register PMCTL */
#define PWM_LDFQ_0    0x1000   /* Load Frequency Bit 0 */  
#define PWM_LDFQ_1    0x2000   /* Load Frequency Bit 1 */  
#define PWM_LDFQ_2    0x4000   /* Load Frequency Bit 2 */  
#define PWM_LDFQ_3    0x8000   /* Load Frequency Bit 3 */  
#define PWM_LDFQ      (PWM_LDFQ_3 | PWM_LDFQ_2 | PWM_LDFQ_1 | PWM_LDFQ_0)   /* Load Frequency Bits [3:0] */  
#define PWM_HALF      0x0800   /* Half Cycle Reload */
#define PWM_IPOL      (PWM_IPOL_0 | PWM_IPOL_1 | PWM_IPOL_2)   /* Current Polarity Bits */  
#define PWM_PRSC_0    0x0040   /* Prescaler Bit 0 */  
#define PWM_PRSC_1    0x0080   /* Prescaler Bit 1 */  
#define PWM_PRSC      (PWM_PRSC_1 | PWM_PRSC_0)   /* Prescaler Bits [1:0] */  
#define PWM_PWMRIE    0x0020   /* Reload Interrupt Enable Bit */
#define PWM_PWMF      0x0010   /* Reload Flag */
#define PWM_ISENS_0   0x0008   /* Current Sense Bit 0 */  
#define PWM_ISENS_1   0x0004   /* Current Sense Bit 1 */  
#define PWM_ISENS     (PWM_ISENS_1 | PWM_ISENS_0) /* Current Sense Bits [1:0] */  
#define PWM_LDOK      0x0002   /* Load Okay Bit */
#define PWM_PWMEN     0x0001   /* PWM Enable Bit */

/* PWM Fault Control Register PMFCTL */
#define PWM_FIE_3         0x0080   /* Fault3 Pin Interrupt Enable Bit */
#define PWM_FIE_2         0x0020   /* Fault2 Pin Interrupt Enable Bit */
#define PWM_FIE_1         0x0008   /* Fault1 Pin Interrupt Enable Bit */
#define PWM_FIE_0         0x0002   /* Fault0 Pin Interrupt Enable Bit */
#define PWM_FMODE_3       0x0040   /* Fault3 Pin Clearing Mode Bit */
#define PWM_FMODE_2       0x0010   /* Fault2 Pin Clearing Mode Bit */
#define PWM_FMODE_1       0x0004   /* Fault1 Pin Clearing Mode Bit */
#define PWM_FMODE_0       0x0001   /* Fault0 Pin Clearing Mode Bit */

/* PWM Fault Status & Acknowledge Register PMFSA */
#define PWM_FTACK_3       0x0040   /* Fault3 Pin Acknowledge Bit */
#define PWM_FTACK_2       0x0010   /* Fault2 Pin Acknowledge Bit */
#define PWM_FTACK_1       0x0004   /* Fault1 Pin Acknowledge Bit */
#define PWM_FTACK_0       0x0001   /* Fault0 Pin Acknowledge Bit */

/* PWM Output Control Register PMOUT */
#define PWM_PAD_EN       0x8000   /* Output Pad Output Enable */
#define PWM_OUTCTL       0x3f00   /* Output Control Enables OUTCTL5-0 */
#define PWM_OUT          0x003f   /* Output Control Bits OUT5-0 */

/* PWM Config Register PMCFG */
#define PWM_EDG          0x1000   /* Edge-Aligned or Center-Aligned PWM's */
#define PWM_TOPNEG45     0x0400   /* Top-side PWM Polarity Bit, channel 4-5 */
#define PWM_TOPNEG23     0x0200   /* Top-side PWM Polarity Bit, channel 2-3 */
#define PWM_TOPNEG01     0x0100   /* Top-side PWM Polarity Bit, channel 0-1 */
#define PWM_TOPNEG       (PWM_TOPNEG45 | PWM_TOPNEG23 | PWM_TOPNEG01)   /* Top-side PWM Polarity Bits, channel 5-0 */
#define PWM_BOTNEG45     0x0040   /* Bottom-side PWM Polarity Bit, channel 4-5 */
#define PWM_BOTNEG23     0x0020   /* Bottom-side PWM Polarity Bit, channel 2-3 */
#define PWM_BOTNEG01     0x0010   /* Bottom-side PWM Polarity Bit, channel 0-1 */
#define PWM_BOTNEG       (PWM_BOTNEG45 | PWM_BOTNEG23 | PWM_BOTNEG01)   /* Bottom-side PWM Polarity Bits, channel 5-0 */
#define PWM_INDEP45      0x0008   /* Independent or Complementary Pair Operation, channel 4-5 */
#define PWM_INDEP23      0x0004   /* Independent or Complementary Pair Operation, channel 2-3 */
#define PWM_INDEP01      0x0002   /* Independent or Complementary Pair Operation, channel 0-1 */
#define PWM_INDEP        (PWM_INDEP45 | PWM_INDEP23 | PWM_INDEP01)   /* Independent or Complementary Pair, channel 5-0 */
#define PWM_WP           0x0001   /* Write Protect Bit */

/* PWM Channel Control Register PMCCR */
#define PWM_ENHA         0x8000   /* Enable Hardware Accelerator */



/***********************************************************************
*
* PWM init
*
***********************************************************************/

#define ioctlPWM_INIT(pPwmBase,param) pwmInit((arch_sPWM*)pPwmBase)

void pwmInit(arch_sPWM *pPwmBase); /* function prototype - implemented in pwm.c */

/***********************************************************************
*
* PWM Control Register
*
***********************************************************************/

#define ioctlPWM_SET_RELOAD_FREQUENCY(pPwmBase,param) \
           { periphBitClear(PWM_LDFQ,(UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg));  \
             periphBitSet((((UWord16)(param)) << 12), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); } 
          

#define ioctlPWM_HALF_CYCLE_RELOAD(pPwmBase,param) \
          if (param) {periphBitSet(PWM_HALF, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg));} \
          else {periphBitClear(PWM_HALF, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg));}  

 
#define ioctlPWM_SET_CURRENT_POLARITY(pPwmBase,param) \
           { periphBitClear(~((((UWord16)(param))) | ((PWM_MAX_INT) & (~(PWM_IPOL_0 | PWM_IPOL_1 | PWM_IPOL_2)))), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); \
             periphBitSet(((UWord16)(param)), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); } 
          

#define ioctlPWM_SET_PRESCALER(pPwmBase,param) \
           { periphBitClear(PWM_PRSC,(UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg));  \
             periphBitSet((((UWord16)(param)) << 6), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); } 
          

#define ioctlPWM_RELOAD_INT(pPwmBase,param) \
          if (param) {periphBitSet(PWM_PWMRIE, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg));} \
          else {periphBitClear(PWM_PWMRIE, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg));}  


#define ioctlPWM_SET_CURRENT_SENSING(pPwmBase,param) \
           { periphBitClear(PWM_ISENS,(UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg));  \
             periphBitSet((((UWord16)(param)) << 2), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg)); } 
          

#define ioctlPWM_DEVICE(pPwmBase,param) \
          if (param) {periphBitSet(PWM_PWMEN, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg));} \
          else {periphBitClear(PWM_PWMEN, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg));}  
          

#define ioctlPWM_CLEAR_RELOAD_FLAG(pPwmBase,param) \
          periphBitClear(PWM_PWMF, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg))


#define ioctlPWM_LOAD_OK(pPwmBase,param) \
           periphBitSet(PWM_LDOK, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ControlReg))
          

/***********************************************************************
*
* PWM Output Control Register
*
***********************************************************************/

#define ioctlPWM_OUTPUT_PAD(pPwmBase,param) \
          if (param) {periphBitSet(PWM_PAD_EN,(UWord16 *)(&((arch_sPWM*)pPwmBase)->OutputControlReg));} \
          else {periphBitClear(PWM_PAD_EN, (UWord16 *)(&((arch_sPWM*)pPwmBase)->OutputControlReg));}  


#define ioctlPWM_OUTPUT_SOFTWARE_CONTROL(pPwmBase,param) \
           { periphBitClear(~(((((UWord16)(param)) << 8)) | ((PWM_MAX_INT) & (~(PWM_OUTCTL)))), (UWord16 *)(&((arch_sPWM*)pPwmBase)->OutputControlReg)); \
             periphBitSet((((UWord16)(param)) << 8), (UWord16 *)(&((arch_sPWM*)pPwmBase)->OutputControlReg)); } 
          

#define ioctlPWM_OUTPUT_CONTROL(pPwmBase,param) \
           { periphBitClear(~((((UWord16)(param))) | ((PWM_MAX_INT) & (~(PWM_OUT)))), (UWord16 *)(&((arch_sPWM*)pPwmBase)->OutputControlReg)); \
             periphBitSet(((UWord16)(param)), (UWord16 *)(&((arch_sPWM*)pPwmBase)->OutputControlReg)); } 

          
/***********************************************************************
*
* PWM Counter Modulo Register
*
***********************************************************************/

#define ioctlPWM_SET_MODULO(pPwmBase,param) \
           periphMemWrite(((UWord16)(param)), (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterModuloReg))
          

#define ioctlPWM_GET_MODULO(pPwmBase,param) \
           periphMemRead( (UWord16 *)(&((arch_sPWM*)pPwmBase)->CounterModuloReg ))

         
/***********************************************************************
*
* PWM Deadtime Register
*
***********************************************************************/

#define ioctlPWM_SET_DEADTIME(pPwmBase,param) \
           periphMemWrite(((UWord16)(param)), (UWord16 *)(&((arch_sPWM*)pPwmBase)->DeadtimeReg))

/**********************************************************************
*
* PWM Config Register
*
***********************************************************************/

#define ioctlPWM_SET_ALIGNMENT(pPwmBase,param) \
          if (param) {periphBitSet(PWM_EDG, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ConfigReg));} \
          else {periphBitClear(PWM_EDG, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ConfigReg));}  


#define ioctlPWM_SET_NEG_TOP_SIDE_POLARITY(pPwmBase,param) \
           { periphBitClear(~(((((UWord16)(param)) << 8)) | ((PWM_MAX_INT) & (~((PWM_CHANNEL_45 | PWM_CHANNEL_23 | PWM_CHANNEL_01) << 8 )))), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ConfigReg)); \
             periphBitSet((((UWord16)(param)) << 8), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ConfigReg)); } 
          

#define ioctlPWM_SET_NEG_BOTTOM_SIDE_POLARITY(pPwmBase,param) \
           { periphBitClear(~(((((UWord16)(param)) << 4)) | ((PWM_MAX_INT) & (~((PWM_CHANNEL_45 | PWM_CHANNEL_23 | PWM_CHANNEL_01) << 4 )))), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ConfigReg)); \
             periphBitSet((((UWord16)(param)) << 4), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ConfigReg)); } 
          

#define ioctlPWM_SET_INDEPENDENT_OPERATION(pPwmBase,param) \
           { periphBitClear(~(((((UWord16)(param)) << 1)) | ((PWM_MAX_INT) & (~((PWM_CHANNEL_45 | PWM_CHANNEL_23 | PWM_CHANNEL_01) << 1 )))), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ConfigReg)); \
             periphBitSet((((UWord16)(param)) << 1), (UWord16 *)(&((arch_sPWM*)pPwmBase)->ConfigReg)); } 


#define ioctlPWM_SET_WRITE_PROTECT(pPwmBase,param) \
           periphBitSet(PWM_WP, (UWord16 *)(&((arch_sPWM*)pPwmBase)->ConfigReg))
          

/**********************************************************************
*
* PWM Channel Control Register
*
***********************************************************************/