📄 adc.h
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* ADC init
***********************************************************************/
#define ioctlADC_INIT(reg,bParam) adcInit((arch_sADC*)reg)
/***********************************************************************
* ADC Control Register
***********************************************************************/
/* start ADC conversion */
#define ioctlADC_START(pAdcBase,param) periphBitSet(ADC_BSTART, \
(UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg)
/* stop ADC conversion */
#define ioctlADC_STOP(pAdcBase,param) \
if (param) periphBitSet(ADC_BSTOP, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg); \
else periphBitClear(ADC_BSTOP, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg)
/* switch on/off ADC conversion starting by SYNC (spec. timer output) */
#define ioctlADC_SYNC(pAdcBase,param) \
if (param) periphBitSet(ADC_BSYNC, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg); \
else periphBitClear(ADC_BSYNC, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg)
/* enable/disable interrupt on the end of the ADC conversion */
#define ioctlADC_END_OF_SCAN_INT(pAdcBase,param) \
if (param) periphBitSet(ADC_EOSIE, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg); \
else periphBitClear(ADC_EOSIE, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg)
/* enable/disable interrupt on ADC zero crossing */
#define ioctlADC_ZERO_CROSS_INT(pAdcBase,param) \
if (param) periphBitSet(ADC_ZCIE, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg); \
else periphBitClear(ADC_ZCIE, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg)
/* enable/disable interrupt on ADC low limit compare */
#define ioctlADC_LOW_LIMIT_INT(pAdcBase,param) \
if (param) periphBitSet(ADC_LLMTIE, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg); \
else periphBitClear(ADC_LLMTIE, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg)
/* enable/disable interrupt on ADC high limit compare */
#define ioctlADC_HIGH_LIMIT_INT(pAdcBase,param) \
if (param) periphBitSet(ADC_HLMTIE, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg); \
else periphBitClear(ADC_HLMTIE, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg)
/* write to CHNCFG[3:0] bits in ADCR1 */
#define ioctlADC_SET_CHANNEL_CONFIG(pAdcBase,param) {periphBitClear(0x00F0, \
(UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg);\
periphBitSet( (((UWord16) (param))<<4) & 0x00F0, \
(UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg);}
/* write to SMODE[2:0] bits in ADCR1 */
#define ioctlADC_SET_SCAN_MODE(pAdcBase,param) \
{periphBitClear(0x0007, (UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg);\
periphBitSet( ((UWord16) param) & 0x0007,(UWord16 *) &((arch_sADC*)pAdcBase)->Control1Reg);}
/* set ADC clock divisor select */
#define ioctlADC_SET_DIVISOR(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->Control2Reg)
/* set ADC zero crossing control register */
#define ioctlADC_WRITE_ZERO_CROSS_CONTROL(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->ZeroCrossControlReg)
/* set ADC channel list register 1 */
#define ioctlADC_WRITE_CHANNEL_LIST1(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->ChannelList1Reg)
/* set ADC channel list register 2 */
#define ioctlADC_WRITE_CHANNEL_LIST2(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->ChannelList2Reg)
/* set ADC channel list register 2 */
//#define ioctlADC_WRITE_SAMPLE_DISABLE(reg,Param) periphMemWrite(Param, \
// (UWord16 *)reg.DisableReg)
#define ioctlADC_WRITE_SAMPLE_DISABLE(pAdcBase,param) {periphBitClear(0x00FF, \
(UWord16 *) &((arch_sADC*)pAdcBase)->DisableReg);\
periphBitSet( (1 << ((UWord16) (param))) & 0x00FF, \
(UWord16 *) &((arch_sADC*)pAdcBase)->DisableReg);}
/* write ADC low limit register x */
#define ioctlADC_WRITE_LOW_LIMIT0(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->LowLimitReg[0])
#define ioctlADC_WRITE_LOW_LIMIT1(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->LowLimitReg[1])
#define ioctlADC_WRITE_LOW_LIMIT2(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->LowLimitReg[2])
#define ioctlADC_WRITE_LOW_LIMIT3(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->LowLimitReg[3])
#define ioctlADC_WRITE_LOW_LIMIT4(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->LowLimitReg[4])
#define ioctlADC_WRITE_LOW_LIMIT5(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->LowLimitReg[5])
#define ioctlADC_WRITE_LOW_LIMIT6(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->LowLimitReg[6])
#define ioctlADC_WRITE_LOW_LIMIT7(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->LowLimitReg[7])
/* set ADC high limit register x */
#define ioctlADC_WRITE_HIGH_LIMIT0(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->HighLimitReg[0])
#define ioctlADC_WRITE_HIGH_LIMIT1(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->HighLimitReg[1])
#define ioctlADC_WRITE_HIGH_LIMIT2(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->HighLimitReg[2])
#define ioctlADC_WRITE_HIGH_LIMIT3(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->HighLimitReg[3])
#define ioctlADC_WRITE_HIGH_LIMIT4(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->HighLimitReg[4])
#define ioctlADC_WRITE_HIGH_LIMIT5(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->HighLimitReg[5])
#define ioctlADC_WRITE_HIGH_LIMIT6(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->HighLimitReg[6])
#define ioctlADC_WRITE_HIGH_LIMIT7(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->HighLimitReg[7])
/* write ADC offset register x */
#define ioctlADC_WRITE_OFFSET0(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->OffsetReg[0])
#define ioctlADC_WRITE_OFFSET1(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->OffsetReg[1])
#define ioctlADC_WRITE_OFFSET2(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->OffsetReg[2])
#define ioctlADC_WRITE_OFFSET3(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->OffsetReg[3])
#define ioctlADC_WRITE_OFFSET4(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->OffsetReg[4])
#define ioctlADC_WRITE_OFFSET5(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->OffsetReg[5])
#define ioctlADC_WRITE_OFFSET6(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->OffsetReg[6])
#define ioctlADC_WRITE_OFFSET7(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->OffsetReg[7])
/* reads samples from result registers */
/* one at a time, param is the number of the Result reg (0-7) */
#define ioctlADC_READ_SAMPLE(pAdcBase,param) periphMemRead( \
(UWord16 *) &((arch_sADC*)pAdcBase)->ResultReg[param])
/* reads samples from result registers - all 8 to the buffer pointed by pParam */
extern void AdcRdResults(adc_tBuff buff, UWord16 *reg);
#define ioctlADC_READ_ALL_SAMPLES(pAdcBase,param) \
AdcRdResults(param, (UWord16 *) &((arch_sADC*)pAdcBase)->ResultReg[0])
/* reads ADC status register */
#define ioctlADC_READ_STATUS(pAdcBase,param) periphMemRead( \
(UWord16 *) &((arch_sADC*)pAdcBase)->StatusReg)
/* test ADC status - conversion in progress bit (CIP) */
#define ioctlADC_GET_STATUS_CIP(pAdcBase,param) periphBitTest(ADC_CIP, \
(UWord16 *) &((arch_sADC*)pAdcBase)->StatusReg)
/* test ADC status - end of scan interrupt flag (EOSI) */
#define ioctlADC_GET_STATUS_EOSI(pAdcBase,param) periphBitTest(ADC_EOSI, \
(UWord16 *) &((arch_sADC*)pAdcBase)->StatusReg)
/* test ADC status - zero crossing interrupt flag (ZCI) */
#define ioctlADC_GET_STATUS_ZCI(pAdcBase,param) periphBitTest(ADC_ZCI, \
(UWord16 *) &((arch_sADC*)pAdcBase)->StatusReg)
/* test ADC status - low limit interrupt flag (LLMTI) */
#define ioctlADC_GET_STATUS_LLMTI(pAdcBase,param) periphBitTest(ADC_LLMTI, \
(UWord16 *) &((arch_sADC*)pAdcBase)->StatusReg)
/* test ADC status - high limit interrupt flag (HLMTI) */
#define ioctlADC_GET_STATUS_HLMTI(pAdcBase,param) periphBitTest(ADC_HLMTI, \
(UWord16 *) &((arch_sADC*)pAdcBase)->StatusReg)
/* test ADC status - ready channel x flag (RDYx), x should be immediate */
/* constant to macro be effective */
#define ioctlADC_GET_STATUS_RDY(pAdcBase,param) periphBitTest(1 << ((UWord16)(param)), \
(UWord16 *) &((arch_sADC*)pAdcBase)->StatusReg)
//#define ioctlADC_GET_STATUS_RDY(pAdcBase,param) periphBitTest(param, \
// (UWord16 *) &((arch_sADC*)pAdcBase)->StatusReg)
//#define ioctlADC_GET_STATUS_RDY(pAdcBase,param) (param) & periphMemRead((UWord16 *) &((arch_sADC*)pAdcBase)->StatusReg )
/* write ADC status register */
#define ioctlADC_WRITE_STATUS(pAdcBase,param) periphMemWrite((UWord16) (param), \
(UWord16 *) &((arch_sADC*)pAdcBase)->StatusReg)
/* most of flag bits in status reg. are cleared by writing "1" to them */
/* clear ADC status bit - end of scan interrupt flag (EOSI) */
#define ioctlADC_CLEAR_STATUS_EOSI(pAdcBase,param) periphBitSet(ADC_EOSI, \
(UWord16 *) &((arch_sADC*)pAdcBase)->StatusReg)
/* reads ADC limit status register - contains all sample limit flag bits */
#define ioctlADC_READ_LIMIT_STATUS(pAdcBase,param) periphMemRead( \
(UWord16 *) &((arch_sADC*)pAdcBase)->LimitReg)
/* test ADC limit status - low limit sample flag x (LLSx) - each sample has distinctive flag bit */
#define ioctlADC_GET_LIMIT_STATUS_LLS(pAdcBase,param) periphBitTest(1 << ((UWord16)(param)), \
(UWord16 *) &((arch_sADC*)pAdcBase)->LimitReg)
/* test ADC limit status - high limit sample flag x (HLSx) - each sample has distinctive flag bit */
#define ioctlADC_GET_LIMIT_STATUS_HLS(pAdcBase,param) periphBitTest(1 << ((UWord16)(param)+8), \
(UWord16 *) &((arch_sADC*)pAdcBase)->LimitReg)
/* reads ADC zero cross status register */
#define ioctlADC_READ_ZERO_CROSS_STATUS(pAdcBase,param) periphMemRead( \
(UWord16 *) &((arch_sADC*)pAdcBase)->ZeroCrossStatusReg)
/* test ADC zero cross status - zero cross sample flag x (ZCSx) */
/* each sample has distinctive flag bit in ZERO_CROSS_STATUS_REG */
#define ioctlADC_GET_ZERO_CROSS_STATUS_ZCS(pAdcBase,param) periphBitTest(1 << ((UWord16)(param)), \
(UWord16 *) &((arch_sADC*)pAdcBase)->ZeroCrossStatusReg)
/* clear ADC status bit - low limit interrupt flag (LLMTI) */
/* cleared indirectly by clearing all LLSx flags in limit status registers */
#define ioctlADC_CLEAR_STATUS_LLMTI(pAdcBase,param) periphBitSet(0x00FF, \
(UWord16 *) &((arch_sADC*)pAdcBase)->LimitReg)
/* clear ADC status bit - high limit interrupt flag (HLMTI) */
/* cleared indirectly by clearing all HLSx flags in limit status registers */
#define ioctlADC_CLEAR_STATUS_HLMTI(pAdcBase,param) periphBitSet(0xFF00, \
(UWord16 *) &((arch_sADC*)pAdcBase)->LimitReg)
/* clear ADC status bit - zero cross interrupt flag (ZCI) */
#define ioctlADC_CLEAR_STATUS_ZCI(pAdcBase,param) periphBitSet(0x00FF, \
(UWord16 *) &((arch_sADC*)pAdcBase)->ZeroCrossStatusReg)
/* clear bits in ADC limit status - low limit sample flag x (LLSx) */
#define ioctlADC_CLEAR_LIMIT_STATUS_LLS(pAdcBase,param) periphBitSet(1 << ((UWord16)(param)), \
(UWord16 *) &((arch_sADC*)pAdcBase)->LimitReg)
/* clear bits in ADC limit status - high limit sample flag x (HLSx) */
#define ioctlADC_CLEAR_LIMIT_STATUS_HLS(pAdcBase,param) periphBitSet(1 << ((UWord16)(param)+8), \
(UWord16 *) &((arch_sADC*)pAdcBase)->LimitReg)
/* clear bits in ADC zero cross status - zero cross sample flag x (ZCSx) */
#define ioctlADC_CLEAR_ZERO_CROSS_STATUS_ZCS(pAdcBase,param) periphBitSet(1 << ((UWord16)(param)), \
(UWord16 *) &((arch_sADC*)pAdcBase)->ZeroCrossStatusReg)
/* reads ADC low limit register x */
#define ioctlADC_READ_LOW_LIMIT(pAdcBase,param) periphMemRead( \
(UWord16 *) &((arch_sADC*)pAdcBase)->LowLimitReg[param])
/* reads ADC high limit register x */
#define ioctlADC_READ_HIGH_LIMIT(pAdcBase,param) periphMemRead( \
(UWord16 *) &((arch_sADC*)pAdcBase)->HighLimitReg[param])
/* reads ADC offset register x */
#define ioctlADC_READ_OFFSET(pAdcBase,param) periphMemRead( \
(UWord16 *) &((arch_sADC*)pAdcBase)->OffsetReg[param])
/****************************************************************************
* Configuration items for appconfig.h (init values, ...),
* should be copied to AppConfig.h
* When item is #undef then ussualy is not initialized
*****************************************************************************/
/* Configuration items for appconfig.h */
/*
// initialization of ADC A
#define ADC_A_CONTROL_REG1 0
#define ADC_A_CONTROL_REG2 0
#define ADC_A_ZERO_CROSS_CONTROL_REG 0
#define ADC_A_CHANNEL_LIST_REG1 0
#define ADC_A_CHANNEL_LIST_REG2 0
#define ADC_A_SAMPLE_DISABLE_REG 0
#define ADC_A_STATUS_REG 0
#define ADC_A_LIMIT_STATUS_REG 0
#define ADC_A_ZERO_CROSS_STATUS_REG 0
// result registers are not initialized
// low limit registers
#define ADC_A_LOW_LIMIT_REG0 0
#define ADC_A_LOW_LIMIT_REG1 0
#define ADC_A_LOW_LIMIT_REG2 0
#define ADC_A_LOW_LIMIT_REG3 0
#define ADC_A_LOW_LIMIT_REG4 0
#define ADC_A_LOW_LIMIT_REG5 0
#define ADC_A_LOW_LIMIT_REG6 0
#define ADC_A_LOW_LIMIT_REG7 0
// high limit registers
#define ADC_A_HIGH_LIMIT_REG0 0
#define ADC_A_HIGH_LIMIT_REG1 0
#define ADC_A_HIGH_LIMIT_REG2 0
#define ADC_A_HIGH_LIMIT_REG3 0
#define ADC_A_HIGH_LIMIT_REG4 0
#define ADC_A_HIGH_LIMIT_REG5 0
#define ADC_A_HIGH_LIMIT_REG6 0
#define ADC_A_HIGH_LIMIT_REG7 0
// offset registers
#define ADC_A_OFFSET_REG0 0
#define ADC_A_OFFSET_REG1 0
#define ADC_A_OFFSET_REG2 0
#define ADC_A_OFFSET_REG3 0
#define ADC_A_OFFSET_REG4 0
#define ADC_A_OFFSET_REG5 0
#define ADC_A_OFFSET_REG6 0
#define ADC_A_OFFSET_REG7 0
// initialization of ADC B - only for DSP56F807
#define ADC_B_CONTROL_REG1 0
#define ADC_B_CONTROL_REG2 0
#define ADC_B_ZERO_CROSS_CONTROL_REG 0
#define ADC_B_CHANNEL_LIST_REG1 0
#define ADC_B_CHANNEL_LIST_REG2 0
#define ADC_B_SAMPLE_DISABLE_REG 0
#define ADC_B_STATUS_REG 0
#define ADC_B_LIMIT_STATUS_REG 0
#define ADC_B_ZERO_CROSS_STATUS_REG 0
// result registers are not initialized
// low limit registers
#define ADC_B_LOW_LIMIT_REG0 0
#define ADC_B_LOW_LIMIT_REG1 0
#define ADC_B_LOW_LIMIT_REG2 0
#define ADC_B_LOW_LIMIT_REG3 0
#define ADC_B_LOW_LIMIT_REG4 0
#define ADC_B_LOW_LIMIT_REG5 0
#define ADC_B_LOW_LIMIT_REG6 0
#define ADC_B_LOW_LIMIT_REG7 0
// high limit registers
#define ADC_B_HIGH_LIMIT_REG0 0
#define ADC_B_HIGH_LIMIT_REG1 0
#define ADC_B_HIGH_LIMIT_REG2 0
#define ADC_B_HIGH_LIMIT_REG3 0
#define ADC_B_HIGH_LIMIT_REG4 0
#define ADC_B_HIGH_LIMIT_REG5 0
#define ADC_B_HIGH_LIMIT_REG6 0
#define ADC_B_HIGH_LIMIT_REG7 0
// offset registers
#define ADC_B_OFFSET_REG0 0
#define ADC_B_OFFSET_REG1 0
#define ADC_B_OFFSET_REG2 0
#define ADC_B_OFFSET_REG3 0
#define ADC_B_OFFSET_REG4 0
#define ADC_B_OFFSET_REG5 0
#define ADC_B_OFFSET_REG6 0
#define ADC_B_OFFSET_REG7 0
*/
#include "adctarget.h"
#endif⌨️ 快捷键说明
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