adc.h

MC56F802BLDC 可以使用的算法 就是电机启动有点慢

/*****************************************************************************
*
* Motorola Inc.
* (c) Copyright 2001 Motorola, Inc.
* ALL RIGHTS RESERVED.
*
******************************************************************************
*
* File Name: adc.h
*
* Description: ADC driver macros and definitions
*
* Modules Included: adctarget.h
*
*****************************************************************************/

#ifndef __ADC_H
#define __ADC_H

/************************************************************
* ADC module identifiers, correspond to module base address
*************************************************************/

#define ADC_A  (&ArchIO.AdcA)
#define ADC_B  (&ArchIO.AdcB)

/***************************************************
* ADC Ioctl commands
****************************************************/
/* command                      |        Param     */

/* ADC control register 1 commands */
#define ADC_INIT                    /* NULL */
#define ADC_START					/* NULL */
#define ADC_STOP					/* ON(1)/OFF(0) */
#define ADC_TEST_MODE 				/* NULL */
#define ADC_SYNC					/* ON(1)/OFF(0) */

#define ADC_END_OF_SCAN_INT			/* interrupt ON(1)/OFF(0) */

#define ADC_ZERO_CROSS_INT			/* interrupt ON(1)/OFF(0) */

#define ADC_LOW_LIMIT_INT			/* interrupt ON(1)/OFF(0) */

#define ADC_HIGH_LIMIT_INT			/* interrupt ON(1)/OFF(0) */

#define ADC_SET_CHANNEL_CONFIG		/* 4-bit config word */
#define ADC_SET_SCAN_MODE   		/* 3-bit mode word */

/* ADC control register 2 set */
#define ADC_SET_DIVISOR 			/* UWord16:4 */

/* write ADC zero cross register */
#define ADC_WRITE_ZERO_CROSS_CONTROL	/* UWord16 : zero cross config bits */

/* write ADC channel list registers */
#define ADC_WRITE_CHANNEL_LIST1		/* UWord16 : sample bits */
#define ADC_WRITE_CHANNEL_LIST2		/* UWord16 : sample bits */
/* write ADC sample disable register */
#define ADC_WRITE_SAMPLE_DISABLE	/* UWord16 : disable mask */

/* read ADC result register */
#define ADC_READ_SAMPLE			    /* sample number 0-7 */

/* read all ADC result registers */
#define ADC_READ_ALL_SAMPLES		/* pointer to buffer (Frac16 *) */

/* mozna pridat funkci (command) pro konverzi Frac vysledku na integer (ASR o 3) */ 

/* read ADC status register */
#define ADC_READ_STATUS 			/* NULL */

/* write ADC low limit registers */
#define ADC_WRITE_LOW_LIMIT0  		/* Frac16 : low limit (sample 0) */
#define ADC_WRITE_LOW_LIMIT1  		/* Frac16 : low limit (sample 1) */
#define ADC_WRITE_LOW_LIMIT2  		/* Frac16 : low limit (sample 2) */
#define ADC_WRITE_LOW_LIMIT3  		/* Frac16 : low limit (sample 3) */
#define ADC_WRITE_LOW_LIMIT4  		/* Frac16 : low limit (sample 4) */
#define ADC_WRITE_LOW_LIMIT5  		/* Frac16 : low limit (sample 5) */
#define ADC_WRITE_LOW_LIMIT6  		/* Frac16 : low limit (sample 6) */
#define ADC_WRITE_LOW_LIMIT7  		/* Frac16 : low limit (sample 7) */

/* write ADC high limit registers */
#define ADC_WRITE_HIGH_LIMIT0 		/* Frac16 : high limit (sample 0) */
#define ADC_WRITE_HIGH_LIMIT1 		/* Frac16 : high limit (sample 1) */
#define ADC_WRITE_HIGH_LIMIT2 		/* Frac16 : high limit (sample 2) */
#define ADC_WRITE_HIGH_LIMIT3 		/* Frac16 : high limit (sample 3) */
#define ADC_WRITE_HIGH_LIMIT4 		/* Frac16 : high limit (sample 4) */
#define ADC_WRITE_HIGH_LIMIT5 		/* Frac16 : high limit (sample 5) */
#define ADC_WRITE_HIGH_LIMIT6 		/* Frac16 : high limit (sample 6) */
#define ADC_WRITE_HIGH_LIMIT7 		/* Frac16 : high limit (sample 7) */

/* write ADC offset registers */
#define ADC_WRITE_OFFSET0	 		/* Frac16 : offset (sample 0) */
#define ADC_WRITE_OFFSET1	 		/* Frac16 : offset (sample 1) */
#define ADC_WRITE_OFFSET2	 		/* Frac16 : offset (sample 2) */
#define ADC_WRITE_OFFSET3	 		/* Frac16 : offset (sample 3) */
#define ADC_WRITE_OFFSET4	 		/* Frac16 : offset (sample 4) */
#define ADC_WRITE_OFFSET5	 		/* Frac16 : offset (sample 5) */
#define ADC_WRITE_OFFSET6	 		/* Frac16 : offset (sample 6) */
#define ADC_WRITE_OFFSET7	 		/* Frac16 : offset (sample 7) */


/* read ADC limit status register */
#define ADC_READ_LIMIT_STATUS 		/* NULL */
/* read ADC zero crossing status register */
#define ADC_READ_ZERO_CROSS_STATUS 	/* NULL */

/* test ADC status register bits - can be used directly in codition */
/* if it is used in assignement then it returns bit value in original position */
#define ADC_GET_STATUS_CIP			/* NULL */
#define ADC_GET_STATUS_EOSI			/* NULL */
#define ADC_GET_STATUS_ZCI			/* NULL */
#define ADC_GET_STATUS_LLMTI		/* NULL */
#define ADC_GET_STATUS_HLMTI		/* NULL */
#define ADC_GET_STATUS_RDY			/* NULL */

/* test ADC limit status register bits */
#define ADC_GET_LIMIT_STATUS_LLS	/* UWord16 : sample number (0-7) */
#define ADC_GET_LIMIT_STATUS_HLS	/* UWord16 : sample number (0-7) */

#define ADC_GET_ZERO_CROSS_STATUS_ZCS	/* UWord16 : sample number (0-7) */

/* clear ADC status registers flags */
//#define ADC_CLEAR_STATUS_CIP		/* NULL */
#define ADC_CLEAR_STATUS_EOSI		/* NULL */
/* clear ADC flags indirectly through clear corresponding reg ADLSTAT, ADZCSTAT */
#define ADC_CLEAR_STATUS_LLMTI		/* NULL */
#define ADC_CLEAR_STATUS_HLMTI		
#define ADC_CLEAR_STATUS_ZCI		

/* clearing bits in Limit Status, Zero Crossing Status reg independently each other */
#define ADC_CLEAR_LIMIT_STATUS_HLS		/* UWord16 : sample number (0-7) */
#define ADC_CLEAR_LIMIT_STATUS_LLS		/* UWord16 : sample number (0-7) */
#define ADC_CLEAR_ZERO_CROSS_STATUS_ZCS	/* UWord16 : sample number (0-7) */ 

/* read ADC low limit register x */
#define ADC_READ_LOW_LIMIT 			/* UWord16: sample number (0-7) */
/* read ADC high limit register x */
#define ADC_READ_HIGH_LIMIT 		/* UWord16: sample number (0-7) */
/* read ADC offset register x */
#define ADC_READ_OFFSET 			/* UWord16: sample number (0-7) */


/****************************************************************************
* ADC constants and type declarations used in the ioctl functions
*****************************************************************************/

#define ADC_ENABLE	1
#define ADC_DISABLE	0

#define ADC_ON	1
#define ADC_OFF	0

/* bit mask for testing of the status registers ADC_READ_STATUS (RDYx bits) */
#define ADC_S0	0x0001
#define ADC_S1	0x0002
#define ADC_S2	0x0004
#define ADC_S3	0x0008
#define ADC_S4	0x0010
#define ADC_S5	0x0020
#define ADC_S6	0x0040
#define ADC_S7	0x0080

/* bit mask for testing of the status registers ADC_READ_LIMIT_STATUS (LLSx, HLSx bits) */
#define ADC_LLS0	0x0001
#define ADC_LLS1	0x0002
#define ADC_LLS2	0x0004
#define ADC_LLS3	0x0008
#define ADC_LLS4	0x0010
#define ADC_LLS5	0x0020
#define ADC_LLS6	0x0040
#define ADC_LLS7	0x0080

#define ADC_HLS0	0x0100
#define ADC_HLS1	0x0200
#define ADC_HLS2	0x0400
#define ADC_HLS3	0x0800
#define ADC_HLS4	0x1000
#define ADC_HLS5	0x2000
#define ADC_HLS6	0x4000
#define ADC_HLS7	0x8000

/* bit masks for registers settings */

/* control register 1 */
#define ADC_BSTOP   0x4000
#define ADC_BSTART  0x2000
#define ADC_BSYNC   0x1000
#define ADC_EOSIE   0x0800    
#define ADC_ZCIE    0x0400    
#define ADC_LLMTIE  0x0200
#define ADC_HLMTIE  0x0100
    
/* status register */
/* - usable also for status register testing with ADC_READ_STATUS */
#define ADC_CIP  	0x8000    
#define ADC_EOSI 	0x0800    
#define ADC_ZCI  	0x0400    
#define ADC_LLMTI   0x0200
#define ADC_HLMTI   0x0100


/* channel list registers - masks for samples & inputs */
/* sample 0 */
#define ADC_AN0_S0	0x0000
#define ADC_AN1_S0	0x0001
#define ADC_AN2_S0	0x0002
#define ADC_AN3_S0	0x0003
#define ADC_AN4_S0	0x0004
#define ADC_AN5_S0	0x0005
#define ADC_AN6_S0	0x0006
#define ADC_AN7_S0	0x0007
/* sample 1 */
#define ADC_AN0_S1	0x0000
#define ADC_AN1_S1	0x0010
#define ADC_AN2_S1	0x0020
#define ADC_AN3_S1	0x0030
#define ADC_AN4_S1	0x0040
#define ADC_AN5_S1	0x0050
#define ADC_AN6_S1	0x0060
#define ADC_AN7_S1	0x0070
/* sample 2 */
#define ADC_AN0_S2	0x0000
#define ADC_AN1_S2	0x0100
#define ADC_AN2_S2	0x0200
#define ADC_AN3_S2	0x0300
#define ADC_AN4_S2	0x0400
#define ADC_AN5_S2	0x0500
#define ADC_AN6_S2	0x0600
#define ADC_AN7_S2	0x0700
/* sample 3 */
#define ADC_AN0_S3	0x0000
#define ADC_AN1_S3	0x1000
#define ADC_AN2_S3	0x2000
#define ADC_AN3_S3	0x3000
#define ADC_AN4_S3	0x4000
#define ADC_AN5_S3	0x5000
#define ADC_AN6_S3	0x6000
#define ADC_AN7_S3	0x7000

/* sample 4 */
#define ADC_AN0_S4	0x0000
#define ADC_AN1_S4	0x0001
#define ADC_AN2_S4	0x0002
#define ADC_AN3_S4	0x0003
#define ADC_AN4_S4	0x0004
#define ADC_AN5_S4	0x0005
#define ADC_AN6_S4	0x0006
#define ADC_AN7_S4	0x0007
/* sample 5 */
#define ADC_AN0_S5	0x0000
#define ADC_AN1_S5	0x0010
#define ADC_AN2_S5	0x0020
#define ADC_AN3_S5	0x0030
#define ADC_AN4_S5	0x0040
#define ADC_AN5_S5	0x0050
#define ADC_AN6_S5	0x0060
#define ADC_AN7_S5	0x0070
/* sample 6 */
#define ADC_AN0_S6	0x0000
#define ADC_AN1_S6	0x0100
#define ADC_AN2_S6	0x0200
#define ADC_AN3_S6	0x0300
#define ADC_AN4_S6	0x0400
#define ADC_AN5_S6	0x0500
#define ADC_AN6_S6	0x0600
#define ADC_AN7_S6	0x0700
/* sample 7 */
#define ADC_AN0_S7	0x0000
#define ADC_AN1_S7	0x1000
#define ADC_AN2_S7	0x2000
#define ADC_AN3_S7	0x3000
#define ADC_AN4_S7	0x4000
#define ADC_AN5_S7	0x5000
#define ADC_AN6_S7	0x6000
#define ADC_AN7_S7	0x7000


/* auxilary definitions */
/*
typedef enum {
    ADC_ZC_DISABLE,
    ADC_ZC_POSITIVE_NEGATIVE,
    ADC_ZC_NEGATIVE_POSITIVE,
    ADC_ZC_ANY
} adc_eZeroCrossing;
*/

/* zero crossing control register - masks for samples and crossing types */
/* sample 0 */
#define ADC_S0_ZC_DISABLE			0x0000
#define ADC_S0_ZC_POSITIVE_NEGATIVE	0x0001
#define ADC_S0_ZC_NEGATIVE_POSITIVE	0x0002
#define ADC_S0_ZC_ANY_CROSS			0x0003
/* sample 1 */
#define ADC_S1_ZC_DISABLE			0x0000
#define ADC_S1_ZC_POSITIVE_NEGATIVE	0x0004
#define ADC_S1_ZC_NEGATIVE_POSITIVE	0x0008
#define ADC_S1_ZC_ANY_CROSS			0x000C
/* sample 2 */
#define ADC_S2_ZC_DISABLE			0x0000
#define ADC_S2_ZC_POSITIVE_NEGATIVE	0x0010
#define ADC_S2_ZC_NEGATIVE_POSITIVE	0x0020
#define ADC_S2_ZC_ANY_CROSS			0x0030
/* sample 3 */
#define ADC_S3_ZC_DISABLE			0x0000
#define ADC_S3_ZC_POSITIVE_NEGATIVE	0x0040
#define ADC_S3_ZC_NEGATIVE_POSITIVE	0x0080
#define ADC_S3_ZC_ANY_CROSS			0x00C0
/* sample 4 */
#define ADC_S4_ZC_DISABLE			0x0000
#define ADC_S4_ZC_POSITIVE_NEGATIVE	0x0100
#define ADC_S4_ZC_NEGATIVE_POSITIVE	0x0200
#define ADC_S4_ZC_ANY_CROSS			0x0300
/* sample 5 */
#define ADC_S5_ZC_DISABLE			0x0000
#define ADC_S5_ZC_POSITIVE_NEGATIVE	0x0400
#define ADC_S5_ZC_NEGATIVE_POSITIVE	0x0800
#define ADC_S5_ZC_ANY_CROSS			0x0C00
/* sample 6 */
#define ADC_S6_ZC_DISABLE			0x0000
#define ADC_S6_ZC_POSITIVE_NEGATIVE	0x1000
#define ADC_S6_ZC_NEGATIVE_POSITIVE	0x2000
#define ADC_S6_ZC_ANY_CROSS			0x3000
/* sample 7 */
#define ADC_S7_ZC_DISABLE			0x0000
#define ADC_S7_ZC_POSITIVE_NEGATIVE	0x4000
#define ADC_S7_ZC_NEGATIVE_POSITIVE	0x8000
#define ADC_S7_ZC_ANY_CROSS			0xC000


#define ADC_AN0_AN1_SE	0
#define ADC_AN2_AN3_SE	0
#define ADC_AN4_AN5_SE	0
#define ADC_AN6_AN7_SE	0

#define ADC_AN0_AN1_DIFF 1
#define ADC_AN2_AN3_DIFF 2
#define ADC_AN4_AN5_DIFF 4
#define ADC_AN6_AN7_DIFF 8

typedef enum {
 ADC_SCAN_ONCE_SEQUENTIAL,
 ADC_SCAN_ONCE_SIMULTANEOUS,
 ADC_SCAN_LOOP_SEQUENTIAL,
 ADC_SCAN_LOOP_SIMULTANEOUS,
 ADC_SCAN_TRIG_SEQUENTIAL,
 ADC_SCAN_TRIG_SIMULTANEOUS
} adc_eScanMode;


/* results buffer */
typedef Frac16 adc_tBuff[8];

void adcInit(arch_sADC *pAdcBase);
//void adcBInit(arch_sADC *pAdcBase);

/****************************************************************************
* ADC ioctl macro functions
*****************************************************************************/

/***********************************************************************