56801_flash-pxrom_int-xram_linker.cmd

MC56F802BLDC 可以使用的算法 就是电机启动有点慢

# ----------------------------------------------------

# Metrowerks, a company of Motorola
# sample code

# linker command file for DSP56801EVM

# using 
#        flash pROM
#        flash xROM
#     internal xRAM 
#         mode 0A
#          EXT 0


# revision history
# 011020 R4.1 A.H. first version
# 030220 R5.1 a.h. improved comments

# ----------------------------------------------------


# see end of file for additional notes
# additional reference: Motorola docs 
#   DSP56F801-7UM.pdf
#   DSP56F801EVMUM.pdf



# memory use for this LCF: 
# interrupt vectors --> flash pROM starting at zero
#      program code --> flash pROM
#         constants --> flash xROM
#      dynamic data --> internal xRAM 



# requirements: Mode 0A and EX=0
# note -- there is a mode OB but any Reset or COP Reset 
#         resets the memory map back to Mode 0A.



# CodeWarrior debugger Target option settings
#    ON --> "Use Hardware Breakpoints" 
#   OFF --> "Debugger sets OMR at Launch" option

# note: since debugger doesn't set OMR, init code's setting is:
# OMR:
#     0 --> EX bit (stay in Debug processing state)
#     0 --> MA bit  
#     0 --> MB bit





# 56801
# mode 0A
# EX = 0

MEMORY 
{
  .p_boot_flash_1       (RX)  : ORIGIN = 0x0000, LENGTH = 0x0004 
  .p_interrupts_ROM     (RX)  : ORIGIN = 0x0004, LENGTH = 0x007C 
  .p_flash_ROM          (RX)  : ORIGIN = 0x0080, LENGTH = 0x1F80
  .p_reserved           (RX)  : ORIGIN = 0x2000, LENGTH = 0x7FFF 	
  .p_internal_RAM       (RWX) : ORIGIN = 0x7C00, LENGTH = 0x0400
  .p_boot_flash_2       (RX)  : ORIGIN = 0x8000, LENGTH = 0x0800 
  .p_reserved_2         (RX)  : ORIGIN = 0x8800, LENGTH = 0x7800 	
  .x_compiler_regs_iRAM (RX)  : ORIGIN = 0x0030, LENGTH = 0x0010 	
  .x_internal_RAM       (RW)  : ORIGIN = 0x0040, LENGTH = 0x03C0
  .x_reserved           (R)   : ORIGIN = 0x0400, LENGTH = 0x0800
  .x_peripherals        (RW)  : ORIGIN = 0x0C00, LENGTH = 0x0400
  .x_flash_ROM          (R)   : ORIGIN = 0x1000, LENGTH = 0x1000
  .x_reserved_2         (R)   : ORIGIN = 0x1800, LENGTH = 0x0800
  .x_external_RAM       (RW)  : ORIGIN = 0x2000, LENGTH = 0xDF80
  .x_core_regs          (RW)  : ORIGIN = 0xFF80, LENGTH = 0x0080
}




# we ensure the interrupt vector sections are not deadstripped here

KEEP_SECTION{ interrupt_vectors.text, interrupt_vectors_mirror }



SECTIONS 
{

	.interrupt_vectors :
	{
	    # from 56801_vector.asm
	    * (interrupt_vectors.text)  
	   
	} > .p_interrupts_ROM



    # hawk mirrors this code back to P memory boot_flash_1

	.interrupt_vectors_mirror :
	{
	    # from 56801_vector_pROM.asm
	    * (interrupt_vectors_mirror.text) 
	   
	} > .p_boot_flash_2



	.executing_code :
	{
		# .text sections
		
		* (.text)
		* (rtlib.text)
		* (fp_engine.text)
		* (user.text)	
	} > .p_flash_ROM
	
	
	
	.x_flash_ROM_data :
	{
	    
		* (.rodata)	 # initialized constants stay in flash xROM
		      
	} > .x_flash_ROM

	
		
	.data : 
	{
	    # data sections
	    
        * (.data)
	    * (fp_state.data)
		* (rtlib.data)
					
		
		
		# .bss sections
		
	  	* (rtlib.bss.lo)
	  	
	  	__bss_start = .;
	  	
		* (.bss)
		
		__bss_end   = .;
		__bss_size = __bss_end - __bss_start;



		# setup the heap address
		
    	__heap_addr = .;
		__heap_size = 0x00C3;
		__heap_end = __heap_addr + __heap_size; 
		
		. = __heap_end;



		# setup the stack address 
		
		_min_stack_size = 0x0200;
		__stack_addr = __heap_end;
		__stack_end  = __stack_addr + _min_stack_size;
		. = __stack_end;
		
		# set global vars now
		
		# MSL uses these globals:		
		F_heap_addr  = __heap_addr;
		F_heap_end   = __heap_end;
		F_stack_addr = __stack_addr;
			
			
			
		# stationery init code globals
		
		F_bss_size      = __bss_size;
		F_bss_addr      = __bss_start;

	} > .x_internal_RAM

  FArchIO   = ADDR(.x_peripherals );
  FArchCore = ADDR(.x_core_regs);

}





# -------------------------------------------------------
# additional notes:



# about the reserved sections
# for this internal RAM and flash ROM LCF:

# p_interrupts_ROM -- reserved in pROM
# memory space reserved for interrupt vectors
# interrupt vectors must start at address zero
# interrupt vector space size is 0x80

# x_compiler_regs_iRAM -- reserved in internal xRAM
# show in memory for clarification
# The compiler uses page 0 address locations 0x30-0x40 
# as register variables. See the Target manual for more info.

# other memory sections are per chip




# LCF notation:
# program memory (p memory)
# (RWX) read/write/execute for pRAM
# (RX) read/execute for flashed pROM

# data memory (X memory)
# (RW) read/write for xRAM
# (R)  read for data flashed xROM

# LENGTH = next start address - previous
# LENGTH = 0x0000 means use all remaing memory