io_map.c

GCC 做的MOTOROLA 的单片机 振荡程序

/** ###################################################################
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : IO_Map.C
**     Project   : LowFreqSG
**     Processor : MC68HC908LV8CFA
**     Beantype  : IO_Map
**     Version   : Driver 01.09
**     Compiler  : CodeWarrior HC08 C Compiler
**     Date/Time : 2006-9-5, 17:47
**     Abstract  :
**         IO_Map.h - implements an IO device's mapping. 
**         This module contains symbol definitions of all peripheral 
**         registers and bits. 
**     Settings  :
**
**     Contents  :
**         No public methods
**
**     (c) Copyright UNIS, spol. s r.o. 1997-2006
**     UNIS, spol. s r.o.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : [e-mail]
** ###################################################################*/
/* Based on CPU DB MC68HC908LV8_52, version 2.89.060 (RegistersPrg V2.05) */
/* DataSheet : MC68HC908LV8 Rev. 2 12/2005 */

#include "PE_types.h"
#include "IO_Map.h"

/*lint -save -esym(765, *) */


/* * * * *  8-BIT REGISTERS  * * * * * * * * * * * * * * * */
volatile PTASTR _PTA;                                      /* Port A Data Register; 0x00000000 */
volatile PTBSTR _PTB;                                      /* Port B Data Register; 0x00000001 */
volatile PTCSTR _PTC;                                      /* Port C Data Register; 0x00000002 */
volatile PTDSTR _PTD;                                      /* Port D Data Register; 0x00000003 */
volatile DDRASTR _DDRA;                                    /* Data Direction Register A; 0x00000004 */
volatile DDRBSTR _DDRB;                                    /* Data Direction Register B; 0x00000005 */
volatile DDRCSTR _DDRC;                                    /* Data Direction Register C; 0x00000006 */
volatile DDRDSTR _DDRD;                                    /* Data Direction Register D; 0x00000007 */
volatile DDRESTR _DDRE;                                    /* Data Direction Register E; 0x00000008 */
volatile PTESTR _PTE;                                      /* Port E Data Register; 0x00000009 */
volatile HDBSTR _HDB;                                      /* Port B High Current Drive Control Register; 0x0000000C */
volatile KBSCRSTR _KBSCR;                                  /* Keyboard Status and Control Register; 0x0000001B */
volatile KBIERSTR _KBIER;                                  /* Keyobard Interrupt Enable Register; 0x0000001C */
volatile CONFIG2STR _CONFIG2;                              /* Configuration Register 2; 0x0000001D */
volatile INTSCRSTR _INTSCR;                                /* IRQ Status and Control Register; 0x0000001E */
volatile CONFIG1STR _CONFIG1;                              /* Configuration Register 2; 0x0000001F */
volatile T1SCSTR _T1SC;                                    /* TIM1 Status and Control Register; 0x00000020 */
volatile T1SC0STR _T1SC0;                                  /* TIM1 Channel Status and Control Register; 0x00000025 */
volatile T1SC1STR _T1SC1;                                  /* TIM1 Channel Status and Control Register; 0x00000028 */
volatile T2SCSTR _T2SC;                                    /* TIM2 Status and Control Register; 0x0000002B */
volatile T2SC0STR _T2SC0;                                  /* TIM2 Channel Status and Control Register; 0x00000030 */
volatile T2SC1STR _T2SC1;                                  /* TIM2 Channel Status and Control Register; 0x00000033 */
volatile PCTLSTR _PCTL;                                    /* PLL Bandwidth Control Register; 0x00000036 */
volatile PBWCSTR _PBWC;                                    /* PLL Bandwidth Control Register; 0x00000037 */
volatile PMRSSTR _PMRS;                                    /* PLL VCO Range Select; 0x0000003A */
volatile PMDSSTR _PMDS;                                    /* PLL Reference Divider Select Register; 0x0000003B */
volatile ADCSCSTR _ADCSC;                                  /* ADC Status and Control Register; 0x0000003C */
volatile ADCLKSTR _ADCLK;                                  /* ADC Input Clock Register; 0x0000003F */
volatile LCDCLKSTR _LCDCLK;                                /* LCD Clock Register; 0x0000004F */
volatile LCDCRSTR _LCDCR;                                  /* LCD Control Register; 0x00000051 */
volatile LDAT1STR _LDAT1;                                  /* LCD Data Register; 0x00000052 */
volatile LDAT2STR _LDAT2;                                  /* LCD Data Register; 0x00000053 */
volatile LDAT3STR _LDAT3;                                  /* LCD Data Register; 0x00000054 */
volatile LDAT4STR _LDAT4;                                  /* LCD Data Register; 0x00000055 */
volatile LDAT5STR _LDAT5;                                  /* LCD Data Register; 0x00000056 */
volatile LDAT6STR _LDAT6;                                  /* LCD Data Register; 0x00000057 */
volatile LDAT7STR _LDAT7;                                  /* LCD Data Register; 0x00000058 */
volatile LDAT8STR _LDAT8;                                  /* LCD Data Register; 0x00000059 */
volatile LDAT9STR _LDAT9;                                  /* LCD Data Register; 0x0000005A */
volatile LDAT10STR _LDAT10;                                /* LCD Data Register; 0x0000005B */
volatile LDAT11STR _LDAT11;                                /* LCD Data Register; 0x0000005C */
volatile LDAT12STR _LDAT12;                                /* LCD Data Register; 0x0000005D */
volatile LDAT13STR _LDAT13;                                /* LCD Data Register; 0x0000005E */
volatile SBSRSTR _SBSR;                                    /* SIM Break Status Register; 0x0000FE00 */
volatile SRSRSTR _SRSR;                                    /* SIM Reset Status Register; 0x0000FE01 */
volatile SBFCRSTR _SBFCR;                                  /* SIM Break Flag Control Register; 0x0000FE03 */
volatile INT1STR _INT1;                                    /* Interrupt Status Register 1; 0x0000FE04 */
volatile INT2STR _INT2;                                    /* Interrupt Status Register 2; 0x0000FE05 */
volatile INT3STR _INT3;                                    /* Interrupt Status Register 3; 0x0000FE06 */
volatile FLCRSTR _FLCR;                                    /* FLASH Control Register; 0x0000FE08 */
volatile BRKSCRSTR _BRKSCR;                                /* Break Status and Control Register; 0x0000FE0E */
volatile LVISRSTR _LVISR;                                  /* LVI Status Register; 0x0000FE0F */
/* FLBPR - macro for reading non volatile register         FLASH1 Block Protect Register; 0x0000FF7E */
volatile COPCTLSTR _COPCTL;                                /* COP Control Register; 0x0000FFFF */


/* * * * *  16-BIT REGISTERS  * * * * * * * * * * * * * * * */
volatile T1CNTSTR _T1CNT;                                  /* TIM1 Counter Register; 0x00000021 */
volatile T1MODSTR _T1MOD;                                  /* TIM1 Counter Modulo Register; 0x00000023 */
volatile T1CH0STR _T1CH0;                                  /* TIM1 Channel Register; 0x00000026 */
volatile T1CH1STR _T1CH1;                                  /* TIM1 Channel Register; 0x00000029 */
volatile T2CNTSTR _T2CNT;                                  /* TIM2 Counter Register; 0x0000002C */
volatile T2MODSTR _T2MOD;                                  /* TIM2 Counter Modulo Register; 0x0000002E */
volatile T2CH0STR _T2CH0;                                  /* TIM2 Channel Register; 0x00000031 */
volatile T2CH1STR _T2CH1;                                  /* TIM2 Channel Register; 0x00000034 */
volatile PMSSTR _PMS;                                      /* PLL Multiplier Select Register; 0x00000038 */
volatile ADRSTR _ADR;                                      /* ADC Data Register; 0x0000003D */
volatile BRKSTR _BRK;                                      /* Break Address Register; 0x0000FE0C */

/*lint -restore */

/* EOF */
/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 2.98 [03.80]
**     for the Freescale HC08 series of microcontrollers.
**
** ###################################################################
*/