📄 io_map.h
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byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} T2SCSTR;
extern volatile T2SCSTR _T2SC @0x0000002B;
#define T2SC _T2SC.Byte
#define T2SC_PS0 _T2SC.Bits.PS0
#define T2SC_PS1 _T2SC.Bits.PS1
#define T2SC_PS2 _T2SC.Bits.PS2
#define T2SC_TRST _T2SC.Bits.TRST
#define T2SC_TSTOP _T2SC.Bits.TSTOP
#define T2SC_TOIE _T2SC.Bits.TOIE
#define T2SC_TOF _T2SC.Bits.TOF
#define T2SC_PS _T2SC.MergedBits.grpPS
#define T2SC_PS0_MASK 0x01
#define T2SC_PS1_MASK 0x02
#define T2SC_PS2_MASK 0x04
#define T2SC_TRST_MASK 0x10
#define T2SC_TSTOP_MASK 0x20
#define T2SC_TOIE_MASK 0x40
#define T2SC_TOF_MASK 0x80
#define T2SC_PS_MASK 0x07
#define T2SC_PS_BITNUM 0x00
/*** T2CNT - TIM2 Counter Register; 0x0000002C ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** T2CNTH - TIM2 Counter Register; 0x0000002C ***/
union {
byte Byte;
} T2CNTHSTR;
#define T2CNTH _T2CNT.Overlap_STR.T2CNTHSTR.Byte
/*** T2CNTL - TIM2 Counter Register; 0x0000002D ***/
union {
byte Byte;
} T2CNTLSTR;
#define T2CNTL _T2CNT.Overlap_STR.T2CNTLSTR.Byte
} Overlap_STR;
} T2CNTSTR;
extern volatile T2CNTSTR _T2CNT @0x0000002C;
#define T2CNT _T2CNT.Word
/*** T2MOD - TIM2 Counter Modulo Register; 0x0000002E ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** T2MODH - TIM2 Counter Modulo Register; 0x0000002E ***/
union {
byte Byte;
} T2MODHSTR;
#define T2MODH _T2MOD.Overlap_STR.T2MODHSTR.Byte
/*** T2MODL - TIM2 Counter Modulo Register; 0x0000002F ***/
union {
byte Byte;
} T2MODLSTR;
#define T2MODL _T2MOD.Overlap_STR.T2MODLSTR.Byte
} Overlap_STR;
} T2MODSTR;
extern volatile T2MODSTR _T2MOD @0x0000002E;
#define T2MOD _T2MOD.Word
/*** T2SC0 - TIM2 Channel Status and Control Register; 0x00000030 ***/
typedef union {
byte Byte;
struct {
byte CH0MAX :1; /* Channel 0 Maximum Duty Cycle Bit */
byte TOV0 :1; /* Toggle-On-Overflow Bit */
byte ELS0A :1; /* Edge/Level Select Bit */
byte ELS0B :1; /* Edge/Level Select Bit */
byte MS0A :1; /* Mode Select Bit A */
byte MS0B :1; /* Mode Select Bit B */
byte CH0IE :1; /* Channel 0 Interrupt Enable Bit */
byte CH0F :1; /* Channel 0 Flag Bit */
} Bits;
struct {
byte :1;
byte grpTOV :1;
byte grpELS0x :2;
byte grpMS0x :2;
byte :1;
byte :1;
} MergedBits;
} T2SC0STR;
extern volatile T2SC0STR _T2SC0 @0x00000030;
#define T2SC0 _T2SC0.Byte
#define T2SC0_CH0MAX _T2SC0.Bits.CH0MAX
#define T2SC0_TOV0 _T2SC0.Bits.TOV0
#define T2SC0_ELS0A _T2SC0.Bits.ELS0A
#define T2SC0_ELS0B _T2SC0.Bits.ELS0B
#define T2SC0_MS0A _T2SC0.Bits.MS0A
#define T2SC0_MS0B _T2SC0.Bits.MS0B
#define T2SC0_CH0IE _T2SC0.Bits.CH0IE
#define T2SC0_CH0F _T2SC0.Bits.CH0F
#define T2SC0_ELS0x _T2SC0.MergedBits.grpELS0x
#define T2SC0_MS0x _T2SC0.MergedBits.grpMS0x
#define T2SC0_CH0MAX_MASK 0x01
#define T2SC0_TOV0_MASK 0x02
#define T2SC0_ELS0A_MASK 0x04
#define T2SC0_ELS0B_MASK 0x08
#define T2SC0_MS0A_MASK 0x10
#define T2SC0_MS0B_MASK 0x20
#define T2SC0_CH0IE_MASK 0x40
#define T2SC0_CH0F_MASK 0x80
#define T2SC0_ELS0x_MASK 0x0C
#define T2SC0_ELS0x_BITNUM 0x02
#define T2SC0_MS0x_MASK 0x30
#define T2SC0_MS0x_BITNUM 0x04
/*** T2CH0 - TIM2 Channel Register; 0x00000031 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** T2CH0H - TIM2 Channel Register; 0x00000031 ***/
union {
byte Byte;
} T2CH0HSTR;
#define T2CH0H _T2CH0.Overlap_STR.T2CH0HSTR.Byte
/*** T2CH0L - TIM2 Channel Register; 0x00000032 ***/
union {
byte Byte;
} T2CH0LSTR;
#define T2CH0L _T2CH0.Overlap_STR.T2CH0LSTR.Byte
} Overlap_STR;
} T2CH0STR;
extern volatile T2CH0STR _T2CH0 @0x00000031;
#define T2CH0 _T2CH0.Word
/* T2CH_ARR: Access 2 T2CHx registers in an array */
#define T2CH_ARR ((volatile word * __far) &T2CH0)
/*** T2SC1 - TIM2 Channel Status and Control Register; 0x00000033 ***/
typedef union {
byte Byte;
struct {
byte CH1MAX :1; /* Channel 1 Maximum Duty Cycle Bit */
byte TOV1 :1; /* Toggle-On-Overflow Bit */
byte ELS1A :1; /* Edge/Level Select Bit */
byte ELS1B :1; /* Edge/Level Select Bit */
byte MS1A :1; /* Mode Select Bit A */
byte :1;
byte CH1IE :1; /* Channel 1 Interrupt Enable Bit */
byte CH1F :1; /* Channel 1 Flag Bit */
} Bits;
struct {
byte :1;
byte grpTOV_1 :1;
byte grpELS1x :2;
byte grpMS1x :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} T2SC1STR;
extern volatile T2SC1STR _T2SC1 @0x00000033;
#define T2SC1 _T2SC1.Byte
#define T2SC1_CH1MAX _T2SC1.Bits.CH1MAX
#define T2SC1_TOV1 _T2SC1.Bits.TOV1
#define T2SC1_ELS1A _T2SC1.Bits.ELS1A
#define T2SC1_ELS1B _T2SC1.Bits.ELS1B
#define T2SC1_MS1A _T2SC1.Bits.MS1A
#define T2SC1_CH1IE _T2SC1.Bits.CH1IE
#define T2SC1_CH1F _T2SC1.Bits.CH1F
#define T2SC1_ELS1x _T2SC1.MergedBits.grpELS1x
#define T2SC1_CH1MAX_MASK 0x01
#define T2SC1_TOV1_MASK 0x02
#define T2SC1_ELS1A_MASK 0x04
#define T2SC1_ELS1B_MASK 0x08
#define T2SC1_MS1A_MASK 0x10
#define T2SC1_CH1IE_MASK 0x40
#define T2SC1_CH1F_MASK 0x80
#define T2SC1_ELS1x_MASK 0x0C
#define T2SC1_ELS1x_BITNUM 0x02
/*** T2CH1 - TIM2 Channel Register; 0x00000034 ***/
typedef union {
word Word;
/* Overlapped registers: */
struct {
/*** T2CH1H - TIM2 Channel Register; 0x00000034 ***/
union {
byte Byte;
} T2CH1HSTR;
#define T2CH1H _T2CH1.Overlap_STR.T2CH1HSTR.Byte
/*** T2CH1L - TIM2 Channel Register; 0x00000035 ***/
union {
byte Byte;
} T2CH1LSTR;
#define T2CH1L _T2CH1.Overlap_STR.T2CH1LSTR.Byte
} Overlap_STR;
} T2CH1STR;
extern volatile T2CH1STR _T2CH1 @0x00000034;
#define T2CH1 _T2CH1.Word
/*** PCTL - PLL Bandwidth Control Register; 0x00000036 ***/
typedef union {
byte Byte;
struct {
byte VPR0 :1; /* VCO Power-of-Two Range Select Bits */
byte VPR1 :1; /* VCO Power-of-Two Range Select Bits */
byte PRE0 :1; /* Prescaler Program Bits */
byte PRE1 :1; /* Prescaler Program Bits */
byte BCS :1; /* Base Clock Select Bit */
byte PLLON :1; /* PLL On Bit */
byte PLLF :1; /* PLL Flag Bit */
byte PLLIE :1; /* PLL Interrupt Enable Bit */
} Bits;
struct {
byte grpVPR :2;
byte grpPRE :2;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} PCTLSTR;
extern volatile PCTLSTR _PCTL @0x00000036;
#define PCTL _PCTL.Byte
#define PCTL_VPR0 _PCTL.Bits.VPR0
#define PCTL_VPR1 _PCTL.Bits.VPR1
#define PCTL_PRE0 _PCTL.Bits.PRE0
#define PCTL_PRE1 _PCTL.Bits.PRE1
#define PCTL_BCS _PCTL.Bits.BCS
#define PCTL_PLLON _PCTL.Bits.PLLON
#define PCTL_PLLF _PCTL.Bits.PLLF
#define PCTL_PLLIE _PCTL.Bits.PLLIE
#define PCTL_VPR _PCTL.MergedBits.grpVPR
#define PCTL_PRE _PCTL.MergedBits.grpPRE
#define PCTL_VPR0_MASK 0x01
#define PCTL_VPR1_MASK 0x02
#define PCTL_PRE0_MASK 0x04
#define PCTL_PRE1_MASK 0x08
#define PCTL_BCS_MASK 0x10
#define PCTL_PLLON_MASK 0x20
#define PCTL_PLLF_MASK 0x40
#define PCTL_PLLIE_MASK 0x80
#define PCTL_VPR_MASK 0x03
#define PCTL_VPR_BITNUM 0x00
#define PCTL_PRE_MASK 0x0C
#define PCTL_PRE_BITNUM 0x02
/*** PBWC - PLL Bandwidth Control Register; 0x00000037 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte ACQ :1; /* Automatic Bandwidth Control Bit */
byte LOCK :1; /* Lock Indicator Bit */
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