📄 io_map.h
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#define DDRC_DDRC4_MASK 0x10
#define DDRC_DDRC5_MASK 0x20
#define DDRC_DDRC6_MASK 0x40
#define DDRC_DDRC7_MASK 0x80
/*** DDRD - Data Direction Register D; 0x00000007 ***/
typedef union {
byte Byte;
struct {
byte DDRD0 :1; /* Data Direction Register D Bit 0 */
byte DDRD1 :1; /* Data Direction Register D Bit 1 */
byte DDRD2 :1; /* Data Direction Register D Bit 2 */
byte DDRD3 :1; /* Data Direction Register D Bit 3 */
byte DDRD4 :1; /* Data Direction Register D Bit 4 */
byte DDRD5 :1; /* Data Direction Register D Bit 5 */
byte DDRD6 :1; /* Data Direction Register D Bit 6 */
byte DDRD7 :1; /* Data Direction Register D Bit 7 */
} Bits;
} DDRDSTR;
extern volatile DDRDSTR _DDRD @0x00000007;
#define DDRD _DDRD.Byte
#define DDRD_DDRD0 _DDRD.Bits.DDRD0
#define DDRD_DDRD1 _DDRD.Bits.DDRD1
#define DDRD_DDRD2 _DDRD.Bits.DDRD2
#define DDRD_DDRD3 _DDRD.Bits.DDRD3
#define DDRD_DDRD4 _DDRD.Bits.DDRD4
#define DDRD_DDRD5 _DDRD.Bits.DDRD5
#define DDRD_DDRD6 _DDRD.Bits.DDRD6
#define DDRD_DDRD7 _DDRD.Bits.DDRD7
#define DDRD_DDRD0_MASK 0x01
#define DDRD_DDRD1_MASK 0x02
#define DDRD_DDRD2_MASK 0x04
#define DDRD_DDRD3_MASK 0x08
#define DDRD_DDRD4_MASK 0x10
#define DDRD_DDRD5_MASK 0x20
#define DDRD_DDRD6_MASK 0x40
#define DDRD_DDRD7_MASK 0x80
/*** DDRE - Data Direction Register E; 0x00000008 ***/
typedef union {
byte Byte;
struct {
byte DDRE0 :1; /* Data Direction Register E Bit 0 */
byte DDRE1 :1; /* Data Direction Register E Bit 1 */
byte DDRE2 :1; /* Data Direction Register E Bit 2 */
byte DDRE3 :1; /* Data Direction Register E Bit 3 */
byte DDRE4 :1; /* Data Direction Register E Bit 4 */
byte DDRE5 :1; /* Data Direction Register E Bit 5 */
byte DDRE6 :1; /* Data Direction Register E Bit 6 */
byte DDRE7 :1; /* Data Direction Register E Bit 7 */
} Bits;
} DDRESTR;
extern volatile DDRESTR _DDRE @0x00000008;
#define DDRE _DDRE.Byte
#define DDRE_DDRE0 _DDRE.Bits.DDRE0
#define DDRE_DDRE1 _DDRE.Bits.DDRE1
#define DDRE_DDRE2 _DDRE.Bits.DDRE2
#define DDRE_DDRE3 _DDRE.Bits.DDRE3
#define DDRE_DDRE4 _DDRE.Bits.DDRE4
#define DDRE_DDRE5 _DDRE.Bits.DDRE5
#define DDRE_DDRE6 _DDRE.Bits.DDRE6
#define DDRE_DDRE7 _DDRE.Bits.DDRE7
#define DDRE_DDRE0_MASK 0x01
#define DDRE_DDRE1_MASK 0x02
#define DDRE_DDRE2_MASK 0x04
#define DDRE_DDRE3_MASK 0x08
#define DDRE_DDRE4_MASK 0x10
#define DDRE_DDRE5_MASK 0x20
#define DDRE_DDRE6_MASK 0x40
#define DDRE_DDRE7_MASK 0x80
/*** PTE - Port E Data Register; 0x00000009 ***/
typedef union {
byte Byte;
struct {
byte PTE0 :1; /* Port E Data Bit 0 */
byte PTE1 :1; /* Port E Data Bit 1 */
byte PTE2 :1; /* Port E Data Bit 2 */
byte PTE3 :1; /* Port E Data Bit 3 */
byte PTE4 :1; /* Port E Data Bit 4 */
byte PTE5 :1; /* Port E Data Bit 5 */
byte PTE6 :1; /* Port E Data Bit 6 */
byte PTE7 :1; /* Port E Data Bit 7 */
} Bits;
} PTESTR;
extern volatile PTESTR _PTE @0x00000009;
#define PTE _PTE.Byte
#define PTE_PTE0 _PTE.Bits.PTE0
#define PTE_PTE1 _PTE.Bits.PTE1
#define PTE_PTE2 _PTE.Bits.PTE2
#define PTE_PTE3 _PTE.Bits.PTE3
#define PTE_PTE4 _PTE.Bits.PTE4
#define PTE_PTE5 _PTE.Bits.PTE5
#define PTE_PTE6 _PTE.Bits.PTE6
#define PTE_PTE7 _PTE.Bits.PTE7
#define PTE_PTE0_MASK 0x01
#define PTE_PTE1_MASK 0x02
#define PTE_PTE2_MASK 0x04
#define PTE_PTE3_MASK 0x08
#define PTE_PTE4_MASK 0x10
#define PTE_PTE5_MASK 0x20
#define PTE_PTE6_MASK 0x40
#define PTE_PTE7_MASK 0x80
/*** HDB - Port B High Current Drive Control Register; 0x0000000C ***/
typedef union {
byte Byte;
struct {
byte PPI1CLKS0 :1; /* PPI1 Clock Source Select Bit 0 */
byte PPI1CLKS1 :1; /* PPI1 Clock Source Select Bit 1 */
byte HDB2 :1; /* Port B LED Drive Enable Bit 2 */
byte HDB3 :1; /* Port B LED Drive Enable Bit 3 */
byte HDB4 :1; /* Port B LED Drive Enable Bit 4 */
byte HDB5 :1; /* Port B LED Drive Enable Bit 5 */
byte PPI1L :1; /* PPI1 Pending for Acknowledgement */
byte :1;
} Bits;
struct {
byte grpPPI1CLKS :2;
byte grpHDB_2 :4;
byte :1;
byte :1;
} MergedBits;
} HDBSTR;
extern volatile HDBSTR _HDB @0x0000000C;
#define HDB _HDB.Byte
#define HDB_PPI1CLKS0 _HDB.Bits.PPI1CLKS0
#define HDB_PPI1CLKS1 _HDB.Bits.PPI1CLKS1
#define HDB_HDB2 _HDB.Bits.HDB2
#define HDB_HDB3 _HDB.Bits.HDB3
#define HDB_HDB4 _HDB.Bits.HDB4
#define HDB_HDB5 _HDB.Bits.HDB5
#define HDB_PPI1L _HDB.Bits.PPI1L
#define HDB_PPI1CLKS _HDB.MergedBits.grpPPI1CLKS
#define HDB_HDB_2 _HDB.MergedBits.grpHDB_2
#define HDB_PPI1CLKS0_MASK 0x01
#define HDB_PPI1CLKS1_MASK 0x02
#define HDB_HDB2_MASK 0x04
#define HDB_HDB3_MASK 0x08
#define HDB_HDB4_MASK 0x10
#define HDB_HDB5_MASK 0x20
#define HDB_PPI1L_MASK 0x40
#define HDB_PPI1CLKS_MASK 0x03
#define HDB_PPI1CLKS_BITNUM 0x00
#define HDB_HDB_2_MASK 0x3C
#define HDB_HDB_2_BITNUM 0x02
/*** KBSCR - Keyboard Status and Control Register; 0x0000001B ***/
typedef union {
byte Byte;
struct {
byte MODEK :1; /* Keyboard Triggering Sensitivity Bit */
byte IMASKK :1; /* Keyboard Interrupt Mask Bit */
byte ACKK :1; /* Keyboard Acknowledge Bit */
byte KEYF :1; /* Keyboard Flag Bit */
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
} KBSCRSTR;
extern volatile KBSCRSTR _KBSCR @0x0000001B;
#define KBSCR _KBSCR.Byte
#define KBSCR_MODEK _KBSCR.Bits.MODEK
#define KBSCR_IMASKK _KBSCR.Bits.IMASKK
#define KBSCR_ACKK _KBSCR.Bits.ACKK
#define KBSCR_KEYF _KBSCR.Bits.KEYF
#define KBSCR_MODEK_MASK 0x01
#define KBSCR_IMASKK_MASK 0x02
#define KBSCR_ACKK_MASK 0x04
#define KBSCR_KEYF_MASK 0x08
/*** KBIER - Keyobard Interrupt Enable Register; 0x0000001C ***/
typedef union {
byte Byte;
struct {
byte KBIE0 :1; /* Keyboard Interrut Enable Bit */
byte KBIE1 :1; /* Keyboard Interrut Enable Bit */
byte KBIE2 :1; /* Keyboard Interrut Enable Bit */
byte KBIE3 :1; /* Keyboard Interrut Enable Bit */
byte PPI1IE0 :1; /* PPI1 Interrupt Period Select Bit 0 */
byte PPI1IE1 :1; /* PPI1 Interrupt Period Select Bit 1 */
byte PPI1IE2 :1; /* PPI1 Interrupt Period Select Bit 2 */
byte :1;
} Bits;
struct {
byte grpKBIE :4;
byte grpPPI1IE :3;
byte :1;
} MergedBits;
} KBIERSTR;
extern volatile KBIERSTR _KBIER @0x0000001C;
#define KBIER _KBIER.Byte
#define KBIER_KBIE0 _KBIER.Bits.KBIE0
#define KBIER_KBIE1 _KBIER.Bits.KBIE1
#define KBIER_KBIE2 _KBIER.Bits.KBIE2
#define KBIER_KBIE3 _KBIER.Bits.KBIE3
#define KBIER_PPI1IE0 _KBIER.Bits.PPI1IE0
#define KBIER_PPI1IE1 _KBIER.Bits.PPI1IE1
#define KBIER_PPI1IE2 _KBIER.Bits.PPI1IE2
#define KBIER_KBIE _KBIER.MergedBits.grpKBIE
#define KBIER_PPI1IE _KBIER.MergedBits.grpPPI1IE
#define KBIER_KBIE0_MASK 0x01
#define KBIER_KBIE1_MASK 0x02
#define KBIER_KBIE2_MASK 0x04
#define KBIER_KBIE3_MASK 0x08
#define KBIER_PPI1IE0_MASK 0x10
#define KBIER_PPI1IE1_MASK 0x20
#define KBIER_PPI1IE2_MASK 0x40
#define KBIER_KBIE_MASK 0x0F
#define KBIER_KBIE_BITNUM 0x00
#define KBIER_PPI1IE_MASK 0x70
#define KBIER_PPI1IE_BITNUM 0x04
/*** CONFIG2 - Configuration Register 2; 0x0000001D ***/
typedef union {
byte Byte;
struct {
byte LVISEL0 :1; /* LVI Operating Mode Selection 0 */
byte LVISEL1 :1; /* LVI Operating Mode Selection 1 */
byte PCEL :1; /* Port C Enable Low Nibble */
byte PCEH :1; /* Port C Enable High Nibble */
byte PDE :1; /* Port D Enable for LCD Drive */
byte PEE :1; /* Port E Enable for LCD Drive */
byte :1;
byte STOP_XCLKEN :1; /* Crystal Oscillator Stop Mode Enable */
} Bits;
struct {
byte grpLVISEL :2;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} MergedBits;
} CONFIG2STR;
extern volatile CONFIG2STR _CONFIG2 @0x0000001D;
#define CONFIG2 _CONFIG2.Byte
#define CONFIG2_LVISEL0 _CONFIG2.Bits.LVISEL0
#define CONFIG2_LVISEL1 _CONFIG2.Bits.LVISEL1
#define CONFIG2_PCEL _CONFIG2.Bits.PCEL
#define CONFIG2_PCEH _CONFIG2.Bits.PCEH
#define CONFIG2_PDE _CONFIG2.Bits.PDE
#define CONFIG2_PEE _CONFIG2.Bits.PEE
#define CONFIG2_STOP_XCLKEN _CONFIG2.Bits.STOP_XCLKEN
#define CONFIG2_LVISEL _CONFIG2.MergedBits.grpLVISEL
#define CONFIG2_LVISEL0_MASK 0x01
#define CONFIG2_LVISEL1_MASK 0x02
#define CONFIG2_PCEL_MASK 0x04
#define CONFIG2_PCEH_MASK 0x08
#define CONFIG2_PDE_MASK 0x10
#define CONFIG2_PEE_MASK 0x20
#define CONFIG2_STOP_XCLKEN_MASK 0x80
#define CONFIG2_LVISEL_MASK 0x03
#define CONFIG2_LVISEL_BITNUM 0x00
/*** INTSCR - IRQ Status and Control Register; 0x0000001E ***/
typedef union {
byte Byte;
struct {
byte MODE :1; /* IRQ Edge/Level Select Bit */
byte IMASK :1; /* IRQ Interrupt Mask Bit */
byte ACK :1; /* IRQ Interrupt Request Acknowledge Bit */
byte IRQF :1; /* IRQ Flag Bit */
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
} INTSCRSTR;
extern volatile INTSCRSTR _INTSCR @0x0000001E;
#define INTSCR _INTSCR.Byte
#define INTSCR_MODE _INTSCR.Bits.MODE
#define INTSCR_IMASK _INTSCR.Bits.IMASK
#define INTSCR_ACK _INTSCR.Bits.ACK
#define INTSCR_IRQF _INTSCR.Bits.IRQF
#define INTSCR_MODE_MASK 0x01
#define INTSCR_IMASK_MASK 0x02
#define INTSCR_ACK_MASK 0x04
#define INTSCR_IRQF_MASK 0x08
/*** CONFIG1 - Configuration Register 2; 0x0000001F ***/
typedef union {
byte Byte;
struct {
byte COPD :1; /* COP Disable Bit */
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